Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device
Reexamination Certificate
2001-06-05
2002-12-10
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
C257S197000, C257S198000, C257S591000, C257S592000
Reexamination Certificate
active
06492664
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a heterojunction bipolar transistor comprising different kinds of joined semiconductors, and a manufacturing method thereof.
(2) Description of the Prior Art
A heterojunction bipolar transistor (HBT) is a transistor for use in compound semiconductor integrated circuits. As an exemplary device structure of the HBT,
FIG. 1
shows a structure of an npn-type HBT with its emitter on the top, and
FIGS. 2
a
to
2
f
illustrate manufacturing steps thereof.
In the first place, as shown in
FIG. 2
a
, subcollector layer
102
, collector layer
103
, base layer
105
, and emitter layer
106
are sequentially formed on insulating substrate
101
by using an epitaxial growth method or the like. Then, a metal film which is to serve as emitter electrode
113
, later described, is deposited over the entire surface thereof.
Next, as shown in
FIG. 2
b
, photoresist
10
of a predetermined pattern is formed on the metal film and used as a mask to process the metal film, thereby providing emitter electrode
113
. Then, photoresist
10
and emitter electrode
113
are used as a mask to remove emitter layer
106
until the surface of base layer
105
is exposed as shown in
FIG. 2
c.
Subsequently, photoresist
10
is removed, and a new photoresist mask of a predetermined pattern is formed on the exposed surface of base layer
105
and used to form base electrode
112
as shown in
FIG. 2
d
through vapor deposition and lift-off procedures. Next, as shown in
FIG. 2
e
, photoresist
11
of a predetermined pattern is formed and used as a mask to remove collector layer
103
until the surface of subcollector layer
102
is exposed.
Then, photoresist
11
is removed and photoresist
12
of a predetermined pattern is formed and used as a mask to inject a predetermined impurity into subcollector layer
102
with an ion implantation technique, thereby forming insulating injection area
114
as shown in
FIG. 2
f.
Finally, photoresist
12
is removed, a photoresist of a predetermined pattern is formed on the exposed surface of subcollector layer
102
and used as a mask to form collector electrode
111
through vapor deposition and lift-off procedures, thereby obtaining the npn-type HBT device in FIG.
1
.
In the aforementioned npn-type HBT, since the junction area (SBC) between base layer
105
and collector layer
103
is larger than the junction area (SBE) between emitter layer
106
and base layer
105
, offset voltage occurs in a three-terminal I-V characteristic as shown in FIG.
3
. In
FIG. 3
, the vertical axis represents collector current I
C
(A) while the horizontal axis represents voltage V
CE
(V) between the collector and the emitter. The offset voltage shown in
FIG. 3
also occurs on conditions as described below.
FIG. 4
is a diagram showing energy bands in an HBT. In the example, difference &Dgr;EBC (=Egc−Egb) between the band gap (Egb) of base layer
302
and the band gap (Egc) of collector layer
303
is smaller than difference &Dgr;EBE (=Ege−Egb) between the band gap (Ege) of emitter layer
301
and the band gap (Egb) of base layer
302
. The offset voltage occurs when &Dgr;EBC<&Dgr;EBE as in the example.
When the aforementioned offset voltage is large, power consumption is greater in a digital IC using an HTB, or power added efficiency is lower in a power amplifier using an HBT, for example.
To avoid the problems, several device structures have been proposed for reducing the offset voltage. As an example,
FIG. 5
shows a cross-sectional structure of an HBT which achieves a reduction in offset voltage. The HBT includes collector layer insulation area
131
obtained by insulating the portion of collector layer
103
in the aforementioned HBT shown in
FIG. 1
which is joined to an outward base area (an area adjacent to an inward base area directly below the emitter layer) of base layer
105
. The provision of collector layer insulation area
131
in collector layer
103
in this manner can reduce the junction area (SBC) between base layer
105
and collector layer
103
to achieve a reduction in the offset voltage.
A structure capable of reducing the offset voltage without using ion implantation is a DHBT (Double Heterojunction Bipolar Transistor).
FIG. 6
shows a cross-sectional structure of such a DHBT. The HBT includes collector layer
141
using a semiconductor with a wide energy band gap instead of collector layer
103
in the structure of the aforementioned HBT shown in FIG.
1
. With the structure, &Dgr;EBE can be equal to &Dgr;EBC to allow a reduction in the offset voltage.
The aforementioned structures of the respective HBTs capable of reducing the offset voltage, however, present problems as below.
In the structure of the HBT shown in
FIG. 5
, since collector layer insulation area
131
is formed by ion-implanting an impurity into the portion joined to the outward base area close to a device intrinsic area, it is conceivable that the impurity can be diffused to the device intrinsic area. Such diffusion of the impurity to the device intrinsic area brings about a lower current gain in an HTPT test (high temperature passage test) to contribute to reduce reliability of the device.
In the structure of the DHBT shown in
FIG. 6
, &Dgr;EBE is equal to &Dgr;EBC and thus &Dgr;EBC causes carriers in operation of the device to be blocked, thereby presenting a problem of reducing collector injection efficiency.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a heterojunction bipolar transistor capable of solving the aforementioned problems, providing high reliability of a device, and reducing offset voltage without reducing collector injection efficiency, and a manufacturing method thereof.
To achieve the aforementioned object, a heterojunction bipolar transistor of the present invention comprises a collector layer, a base layer, and an emitter layer stacked sequentially, wherein the base layer comprises a first base layer joined to the collector layer in an inward base area directly below the emitter layer and a second base layer joined to the collector layer in an outward base area adjacent to the inward base area. The second base layer is formed of a semiconductor with a wider energy band gap than the collector layer.
A method of manufacturing a heterojunction bipolar transistor comprises a first step of sequentially stacking a collector layer, a first base layer, and an emitter layer, a second step of removing the first base layer in an outward base area adjacent to an inward base area directly below the emitter layer and a portion of the collector layer directly below the outward base area, and a third step of forming an insulating film made of a predetermined material on the entire surface of the inward base area to sequentially form a second base layer made of a semiconductor with a wider energy band gap than the collector layer and the first base layer on the collector layer from which the portion has been removed in the second step through selective re-growth by using the insulating film.
Another method of manufacturing a heterojunction bipolar transistor comprises a first step of sequentially stacking a collector layer and a first base layer made of a semiconductor with a wider energy band gap than the collector, a second step of forming an insulating film made of a predetermined material on the entire surface of the first base layer and removing the first base layer in an inward base area directly below an emitter layer to be formed on the first base layer and the insulating film on the inward base area to expose a surface of the collector layer, a third step of re-growing a second collector layer on the surface of the collector layer exposed in the second step, and a fourth step of removing the insulating film and then sequentially forming a second base layer made of a predetermined material and the emitter layer made of a semiconductor with a wider energy band gap than the second base layer through re-growth.
As described a
Ho Hoai
Katten Muchin Zavis & Rosenman
NEC Corporation
Tran Mai-Huong
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