Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
1999-07-21
2002-03-12
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S198000, C257S199000, C257S200000, C257S201000
Reexamination Certificate
active
06355947
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a bipolar transistor and a method of manufacturing the bipolar transistor, and more particularly to a heterojunction bipolar transistor (HBT) in which parasitic emitter resistance is effectively reduced.
BACKGROUND OF THE INVENTION
Conventionally, in order to reduce emitter resistance of a heterojunction bipolar transistor, there is known a method in which a composition graded layer, i.e., a layer in which the composition is graded, sloped or inclined is inserted between an emitter cap layer and an emitter layer, and thereby an increase in the emitter resistance caused by the discontinuity of a conduction band is suppressed. Such method is described, for example, in a thesis “High Performance InGaP/GaAs HBTs with AlGaAs/InGaP Emitter Passivated Ledges for Reliable Power Applications”, TuP24, Digest Book of International Electron Device Meeting 1997, page 361.
An explanation will be made in detail on a structure of a conventional HBT which uses an InGaP layer as an emitter layer and which adopts the above-mentioned method to reduce emitter resistance.
FIG. 9
is a sectional view illustrating an example of a epitaxial layer structure of a conventional HBT which uses an InGaP emitter layer. In the structure of
FIG. 9
, n type GaAs subcollector layer
2
, n type GaAs collector layer
3
, and p type InGaAs composition graded base layer
4
are sequentially formed or laminated on a semi-insulating GaAs substrate
1
which is hereafter referred to also as a semi-insulating substrate. The n type GaAs subcollector layer
2
is hereafter referred to also as an n type collector contact layer, and the n type GaAs collector layer
3
is hereafter referred to also as an n type collector layer. The p type InGaAs composition graded layer
4
is referred to also as a “base layer
4
” or a “layer
4
” hereafter. On a part of the n type GaAs subcollector layer
2
and on a part of the base layer
4
, a collector electrode
10
and a base electrode
11
are respectively formed by vapor deposition. On the base layer
4
, an n type InGaP emitter layer
5
is formed. Hereafter, the n type InGaP emitter layer
5
is also referred to as an n type emitter layer
5
, an emitter layer
5
or a layer
5
. On the emitter layer
5
, an n type AlGaAs composition graded layer
6
, in which Al composition is graded, is formed. Hereafter, the n type AlGaAs composition graded layer
6
is referred to also as a layer
6
. The impurity concentration of each of the layer
5
and the layer
6
is set to a low value to avoid increase in the base-emitter capacity, and is set to a value between 1×10
17
cm
−3
and 5×10
17
cm
−3
. The layer
6
is provided to avoid occurrence of discontinuity of the conduction band between the n type InGaP emitter layer
5
and an n type GaAs cap layer
8
, stacked on the layer
6
, and thereby to suppress increase in the emitter resistance. Hereafter, the n type GaAs cap layer
8
is also referred to as the “layer
8
”. An n type composition graded InGaAs contact layer
9
which is stacked on the layer
8
and which is hereafter referred to also as “layer
9
” is used to decrease contact resistance between an emitter electrode
12
stacked on the layer
9
and the layer
8
. Both the layer
8
and the layer
9
are set to have a high impurity concentration equal to or larger than 1×10
18
cm
−3
to decrease resistance thereof.
FIG. 10
shows a distribution of impurity concentration and a distribution of Al composition from the layer
5
to the layer
9
in the conventional heterojunction bipolar transistor shown in FIG.
9
.
A hetero guard ring portion
13
is provided to protect the surface of the base layer
4
between the base electrode
11
and the emitter electrode
12
. By providing the hetero guard ring
13
, it becomes possible to greatly decrease the surface recombination current at the surface of the base layer
4
. The hetero guard ring portion
13
can be formed, after etching the layer
9
, by selectively etching the layer
8
by means of selective dry etching of AlGaAs/GaAs and by leaving the layer
6
. It is necessary that the hetero guard ring portion
13
is completely depleted. Therefore, when, for example, the total thickness of the layer
5
and the layer
6
is 60 nm, it is necessary that the impurity concentration of layer
6
as well as the layer
5
is set to at most a value equal to or lower than 5×10
17
cm
−3
.
Now, explanation will be made as to the reasons why the emitter resistance, i.e., the resistance from the interface between the layer
5
and the base layer
4
to the emitter electrode
12
, is high in the above-mentioned prior art HBT structure.
In the HBT structure shown in
FIG. 9
, a composition graded layer is used and, therefore, potential barrier caused by the discontinuity of conduction band does not occur. However, the emitter resistance becomes large by the reasons mentioned below.
In
FIG. 11
, a solid line shows a characteristic of a differential resistivity of an emitter from the layer
5
to the layer
9
in the conventional HBT. The ordinate designates differential resistivity in ohm/micrometer, and the abscissa designates distance or position between the layer
5
and the layer
9
in micrometer. The area of the emitter is
10
square micrometers. The differential resistivity r(x) is represented by the expression (1) below. In the graph of
FIG. 11
, the area of a portion surrounded by the curve the differential resistivity r(x) and the abscissa becomes equal to the emitter resistance Re.
Re=∫r
(
x
)
dx
(1)
In
FIG. 11
, the dotted line shows a characteristic of a differential resistivity of a bulk calculated from the sheet resistances of the layer
5
and the layer
6
. In the graph of
FIG. 11
, when the area surrounded by the solid line and the abscissa, that is, the emitter resistance, is compared with the area surrounded by the dotted line and the abscissa, that is, the bulk resistance, it can be seen that the emitter resistance becomes higher than the bulk resistance in the vicinity of the n type AlGaAs composition graded layer
6
.
The reason why the differential resistivity becomes higher from the layer
6
toward the layer
5
is as follows. Since, in the layer
6
, electron affinity varies with the gradient of composition, charge transfer occurs in the layer
6
and electron concentration reduces locally in the vicinity of the interface between the layer
6
and the layer
5
.
FIG. 12
shows a distribution of electron concentration from the layer
5
to the layer
9
of the conventional HBT. From
FIG. 12
, it can be seen that electron concentration becomes high on the side of the layer
8
in the layer
6
, and on the other hand electron concentration reduces in the vicinity of the interface between the layer
6
and the layer
5
.
In the conventional structure shown in
FIG. 9
, there is a disadvantage in that the emitter resistance, that is, a resistance from the interface between the layer
5
and the base layer
4
to the emitter electrode
12
, is considerably higher than the sum of bulk resistance calculated from the sheet resistance from the layer
5
to the layer
9
constituting an emitter and contact resistance between the electrode
12
and the layer
9
. This is because, in the n type AlGaAs composition graded layer
6
, electron affinity decreases according to the increase in Al composition toward the n type InGaP emitter layer
5
. Due to such decrease in electron affinity, electron concentration within the layer
6
greatly decreases toward the n type InGaP emitter layer
5
, and, due to the decrease in the electron concentration, a high resistance portion is produced in the vicinity of the interface between the layer
6
and the layer
5
.
SUMMARY OF THE INVENTION
It is a main object of the present invention to provide a heterojunction bipolar transistor whose emitter resistance is made lower than that of a conventional heterojunction bipolar transistor.
It is another ob
Dickey Thomas L
McGinn & Gibb PLLC
Tran Minh Loan
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