Heterogeneous transceiver architecture for wide range...

Multiplex communications – Communication techniques for information carried in plural...

Reexamination Certificate

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C370S518000, C370S536000, C370S465000, C370S468000, C370S503000, C370S373000, C370S376000

Reexamination Certificate

active

07616657

ABSTRACT:
High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

REFERENCES:
patent: 6650638 (2003-11-01), Walker et al.
patent: 6724328 (2004-04-01), Lui et al.
patent: 6750675 (2004-06-01), Venkata et al.
patent: 6946873 (2005-09-01), Sendrovitz
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2003/0052709 (2003-03-01), Venkata et al.
patent: 2004/0042504 (2004-03-01), Khoury et al.
patent: 1 248 372 (2002-10-01), None

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