Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2001-03-28
2003-04-22
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S012000, C257S015000, C257S020000, C257S085000, C257S094000, C257S183000, C257S184000, C257S185000, C257S187000, C257S190000, C257S192000, C257S192000, C257S194000, C257S195000, C257S196000, C257S201000
Reexamination Certificate
active
06552373
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a hetero-junction field effect transistor (hereinafter abbreviated as HJFET) having an intermediate layer and, more particularly, to a HJFET having higher output power and excellent low-noise performance.
(b) Description of the Related Art
FIG. 1
schematically shows a conventional HJFET. Such a structure of HJFET is reported, for example, by T. Egawa, et al. on International Electron Device Meeting Digest, 1999.
The HJFET has a buffer layer
201
made of gallium nitride (GaN), a GaN channel layer
202
, an AlGaN electron supply layer
203
and an n-type GaN cap layer
205
which are stacked consecutively on a sapphire substrate
200
. A source electrode
8
S and a drain electrode
8
D are formed on the n-type GaN cap layer
205
while making an ohmic contact therewith. A gate electrode
9
is formed in contact with the AlGaN layer
203
while making a Schottky contact therewith, in a recess
17
which is formed by removing part of the n-type GaN cap layer
205
and the AlGaN electron supply layer
203
.
In the hetero-structure described above, it is known that polarized charges are generated due to piezoelectric polarization effect because the lattice constant (‘a’ axis) of AlGaN is smaller than that of GaN, and also due to the spontaneous polarization effect because the atomic arrangement of AlGaN deviates from the ideal arrangement even in the state free of strain.
FIG. 1B
shows the charge distribution between the channel layer
202
and the cap layer
205
of the HJFET of the prior art. During Ga surface growth, polarized positive charge +&sgr;
POL
is generated in channel side hetero-interface and polarized negative charge −&sgr;
POL
is generated in cap side hetero-interface. As a result, two-dimensional electrons are induced resulting in the generation of negative charge −&sgr;
2DEG
in the channel side hetero-interface, while a depletion layer is formed resulting in the generation of positive charges +&sgr;
DON
in the cap layer
205
.
FIG. 1C
is an energy band diagram showing the energy distribution in the conduction band corresponding to
FIG. 1B
, in which energy is plotted along the ordinate and depth is plotted along the abscissa. Quantum well is formed in the channel side hetero-interface so that two-dimensional electrons are generated therein, while the depletion layer is formed in the cap side hetero-interface so that a potential barrier against electrons is formed therein.
A numerical computation shows that the magnitude of the potential barrier formed in the cap side hetero-interface is 0.9 eV when the value of Al proportion y in the AlGaN layer
203
is 0.2, and reaches 3 eV when y is 0.4. Due to the effect of the potential barrier, the probability of tunneling of electrons to pass between the cap layer
205
and the channel layer
202
decreases. Consequently, when an ohmic electrode is formed through contact with the GaN layer
205
, contact resistance increases, thereby making it impossible to decrease the source resistance and the drain resistance sufficiently. Thus there are such problems that the power gain decreases, power delivering efficiency for a large signal amplitude decreases, and the noise factor increases.
SUMMARY OF THE INVENTION
With the background described above, it is an object of the present invention to provide a heterojunction field effect transistor which has lower source resistance, lower drain resistance, higher output power and excellent noise characteristic.
The present invention provides in a first aspect thereof, a hetero-junction field effect transistor (HJFET) including a substrate, a layer structure including an In
x
Ga
1−x
N (0≦x≦1) channel layer, an Al
y
Ga
1−y
N (0<y≦1) electron supply layer, at least one intermediate layer and an n-type GaN cap layer consecutively formed on the substrate, a gate electrode disposed in contact with the electron supply layer, and source and drain electrodes disposed in contact with the n-type cap layer, the at least one intermediate layer being formed as a single n-type-impurity doped layer or a plurality of stacked layers including at least one n-type-impurity doped layer.
The present invention provides, in a second aspect thereof, a hetero-junction field effect transistor (HJFET) including a substrate, a layer structure including an In
x
Ga
1−x
N (0≦x≦1) channel layer, an Al
y
Ga
1−y
N (0<y≦1) electron supply layer, at least one intermediate layer and an n-type In
u
Ga
1−u
N cap layer consecutively formed on the substrate, a gate electrode disposed in contact with the electron supply layer, and source and drain electrodes disposed in contact with the n-type cap layer, the at least one intermediate layer being formed as a single n-type-impurity doped layer or a plurality of stacked layers including at least one n-type-impurity doped layer.
In accordance with the HJFET of the first and second aspects of the present invention, the intermediate layer cancels the polarized negative charges generated between the electron supply layer and the n-type cap layer by ionized positive charges, whereby the hetero-junction field effect transistor of the present invention has the advantages of reduction of the source/drain resistance, a higher output power and an excellent noise characteristic.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 5670798 (1997-09-01), Shetzina
patent: 5679965 (1997-10-01), Schetzina
patent: 5739554 (1998-04-01), Edmond et al.
patent: 5880486 (1999-03-01), Nakamura et al.
patent: 6031858 (2000-01-01), Hatakoshi et al.
patent: 6064082 (2000-05-01), Kawai et al.
patent: 6274893 (2001-08-01), Igarashi et al.
patent: 6285698 (2001-09-01), Romano et al.
patent: 6316793 (2001-11-01), Sheppard et al.
patent: 6323053 (2001-11-01), Nishikawa et al.
patent: 2001/0017370 (2001-08-01), Sheppard et al.
Ando Yuji
Hayama Nobuyuki
Iwata Naotaka
Kasahara Kensuke
Kunihiro Kazuaki
NEC Corporation
Soward Ida M.
Sughrue & Mion, PLLC
Zarabian Amir
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