Hetero-junction field effect transistor

Details Hetero-junction field effect transistor Hetero-junction field effect transistor

1999-02-01

2001-07-03

Mintel, William (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

C257S194000, C257S195000, C438S172000

Reexamination Certificate

active

06255673

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a hetero-junction field effect transistor, and more particularly to a hetero-junction field effect transistor having a smaller gate breakdown voltage and a smaller parasitic resistance.
2. Description of the Related Art
A field effect transistor (hereinafter, referred to simply as “FET”) composed of compound semiconductor such as GaAs, is known to those skilled in the art as a high-powered transistor operating in a high frequency band. Among FETs, a schottky barrier metal-semiconductor junction type field effect transistor (hereinafter, referred to simply as “MESFET”) has been widely put into practice. A MESFET is characterized by that a schottky layer, in with which schottky barrier metal makes contact, is composed of the same semiconductor such as GaAs, as the semiconductor of which a channel layer through which a channel current runs is composed.
A hetero-junction field effect transistor (hereinafter, referred to simply as “HFET”) is also known to those skilled in the art as a transistor characterized by that a schottky layer is composed of semiconductor different from the semiconductor of which the channel layer is composed, as suggested, for instance, in Japanese Unexamined Patent Publication No. 5-47798 based on U.S. patent application Ser. No. 07/648091 filed by Paul Sania et al. on Jan. 27, 1992, and assigned to Texas Instruments Incorporated.
FIG. 1
is a cross-sectional view of a conventional HFET. The illustrated HFET is comprised of a semi-insulating GaAs substrate
11
, a buffer layer
12
formed on the GaAs substrate
11
, an n-type GaAs channel layer
13
formed on the buffer layer
12
, an n-type AlGaAs schottky layer
14
formed on the n-type GaAs channel layer
13
, an n-type GaAs contact layer
15
formed on the n-type AlGaAs schottky layer
14
and formed with a recess
15
a
, a gate electrode
18
formed on the schottky layer
14
in the recess
15
a
, and a source electrode
17
and a drain electrode
19
both formed on the n-type GaAs contact layer
15
so that the gate electrode
18
is located between the source and drain electrodes
17
and
19
.
In a HFET, a channel layer is composed of a first semiconductor having high electron mobility, such as GaAs, whereas a schottky layer is composed of a second semiconductor different from the first semiconductor and including a forbidden band having a great width, such as AlGaAs. Hence, the HFET could have a higher gate breakdown voltage with a maximum drain current allowed to run therethrough being kept constant.
An advantage of a HFET in which a greater amount of drain current and a higher gate breakdown voltage can be both obtained, is that the HFET is then suitable in particular for a micro-wave high-powered transistor.
In a conventional HFET as illustrated in
FIG. 1
, it was necessary for the n-type AlGaAs schottky layer
14
to have a relatively low impurity concentration in order to keep a gate breakdown voltage high. For instance, the n-type AlGaAs schottky layer
14
had to have an impurity concentration in the range of 5×10
16
to 2×10
17
cm
−3
. This is because if the schottky layer had a high impurity concentration, the greater number of electrons would flow into semiconductor from a gate metal by virtue of the quantum tunnel effect, resulting in a reduction in a gate breakdown voltage.
On the other hand, it was necessary for electrons to be transferred vertically through the n-type GaAs channel layer
13
, through the n-type AlGaAs schottky layer
14
, and through the n-type GaAs contact layer
15
to avoid electrical resistance in regions located below the source and drain electrodes
17
and
19
. That is, a conventional HFET is accompanied with a problem that, as shown in
FIG. 2
, an energy band diagram, if the n-type AlGaAs schottky layer
14
has a relatively low impurity concentration, then a potential barrier over which electrons have to jump would be higher, which means that electrical resistance to electrons would be higher.
Since parasitic resistance in a region located below the source electrode
17
has a disadvantage of reducing mutual conductance which is quite important for the amplifying performance of FET, it is quite important to reduce such parasitic resistance.
In brief, a conventional HFET is accompanied by the problem that it is not possible to reduce a parasitic resistance, such as source or drain resistance, in the FET without also reducing the gate breakdown voltage.
Japanese Unexamined Patent Publication No. 5-152339 published on Jun. 18, 1993 has suggested a field effect transistor comprising a GaAs substrate, a GaAs layer formed on the GaAs substrate, a first n-type GaAs layer formed on the GaAs layer, a non-doped InGaAs layer formed on the first n-type GaAs layer, a second n-type GaAs layer formed on the non-doped InGaAs layer, a gate electrode formed on an exposed surface of the first n-type GaAs layer in a recess formed through the second n-type GaAs layer and the non-doped InGaAs layer, and source and drain electrodes both formed on the second n-type GaAs layer so that the gate electrode is located between the source and drain electrodes.
Japanese Unexamined Patent Publication No. 8-222578 published on Aug. 30, 1996 has suggested a field effect transistor comprising a non-doped InAlAs layer, a p-type InAlAs layer, a non-doped InAlAs layer, a non-doped InGaAs layer, a non-doped InAlAs layer, an n-type InAlAs layer, a non-doped InAlAs layer, an n-type InAlAs layer, and an n-type InGaAs layer, all of which are formed on a semi-insulating substrate in this order. A gate electrode is formed having a depth reaching the non-doped InAlAs layer. Source and drain electrodes are formed on the n-type InGaAs layer. A highly p-type impurity doped region is formed through the non-doped InAlAs layer, the non-doped InGaAs layer, the non-doped InAlAs layer, the n-type InAlAs layer, the non-doped InAlAs layer, the n-type InAlAs layer and the n-type InGaAs layer, reaching the p-type InAlAs layer. An ohmic electrode is formed on the highly p-type impurity doped region.
Japanese Unexamined Patent Publication No. 9-45894 published on Feb. 14, 1997 has suggested a method of fabricating a field effect transistor, comprising the steps of forming an i-GaAs buffer layer, an InGaAs electron transit layer, an n-type AlGaAs electron donating layer, an n-type InGaP spacer layer, and an n
+
-type GaAs contact layer on a semi-insulating GaAs substrate in this order, forming source and drain electrodes, forming a photoresist film formed with an opening having a second recess pattern, etching the n
+
-type GaAs contact layer with the photoresist film being used as a mask, etching the n-type InGaP spacer layer in a selected area to thereby form a first recess, side-etching the n
+
-type GaAs contact layer in a selected area to thereby form the second recess, and forming a gate electrode by means of aluminum evaporation and lift-off.
However, the above-mentioned Publications are all accompanied with the problem mentioned earlier that they cannot reduce parasitic resistance such as source or drain resistance without reducing the gate breakdown voltage.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a field effect transistor capable of having a higher gate breakdown voltage and lower source and drain resistances.
There is provided a hetero-junction field effect transistor including (a) a buffer layer formed on a substrate, (b) a channel layer formed on the buffer layer and composed of a first semiconductor containing n-type impurity therein at least partially in a thickness-wise direction thereof, (c) a schottky layer formed on the channel layer and composed of a second semiconductor including a forbidden band having a greater width than a width of a forbidden band of the first semiconductor, (d) an electron donating layer formed on the schottky layer and having smaller electron affinity than that of the channel layer, (e) a contact layer formed on the electron

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