Hetero field effect transistor and manufacturing method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor

Reexamination Certificate

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C257S194000, C257S196000, C257SE29246

Reexamination Certificate

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07868355

ABSTRACT:
A hetero field effect transistor includes: a main semiconductor region including a first semiconductor layer and a second semiconductor layer formed thereon to allow a generation of a two-dimensional carrier gas layer of a first conductive type on a heterojunction interface therebetween; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on the second semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode formed on the third semiconductor layer. A concave portion is formed in an upper surface of the second semiconductor layer at a region immediately below the gate electrode.

REFERENCES:
patent: 2007/0170463 (2007-07-01), Ueno et al.
patent: 2006339561 (2006-12-01), None
patent: 2007019309 (2007-01-01), None

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