HEMT type semiconductor device having two semiconductor well lay

Details HEMT type semiconductor device having two semiconductor well lay HEMT type semiconductor device having two semiconductor well lay

1992-06-17

1994-04-12

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257 11, 257 20, 257 24, 257 27, 257192, 257615, 257631, 257914, H01L 29161, H01L 29205, H01L 29225

Patent

active

053028406

ABSTRACT:
A HEMT type semiconductor device includes a semiconductor substrate, a buffer semiconductor layer formed on the substrate, a first semiconductor well layer formed on the buffer layer and serving as a first conductivity type channel layer, a second semiconductor well layer formed on the first well layer and serving as a second conductivity type opposite the first conductivity, a channel layer and a potential barrier layer formed on the second well layer and forming a potential barrier for carriers. The substrate is made of GaAs or InP, and the layers are successively and epitaxially grown on the substrate. A two dimensional hole gas and a two dimensional electron gas are confined in the first well layer and in the second well layer, respectively.

REFERENCES:
patent: 4236165 (1980-11-01), Kawashima et al.
patent: 4807001 (1989-02-01), Hida
patent: 4942438 (1990-07-01), Miyamoto
patent: 5049951 (1991-09-01), Goronkin et al.
patent: 5060031 (1991-10-01), Abrokwah et al.
Akinwande et al., "Complementary III-V Heterostructure FETs for Low Power Integrated Circuits", IEEE 1990 (IEDM90), pp. 983-986.
Daniels et al., "Complementary Hetrostructure Insulated Gate FET Circuits for High-Speed, Low Power VLSI", IEEE 1986 (IEDM86), pp. 448-451.
WO-A-8 901 704, Published Feb. 23, 1989; (Regents of the University of Minnesota) *p. 14, lines 9-24; FIGS. 12A, 12B*.

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