Heat-treating methods and systems

Details Heat-treating methods and systems Heat-treating methods and systems

2000-12-04

2003-07-15

Walberg, Teresa (Department: 3742)

Electric resistance heating devices

Heating devices

Radiant heater

C219S390000, C219S121600, C219S388000, C219S405000, C392S418000, C392S423000, C118S724000, C118S050100

Reexamination Certificate

active

06594446

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to heating of objects, and more particularly to methods and systems for heat-treating a workpiece.
BACKGROUND OF THE INVENTION
Many applications require heating or annealing of an object or workpiece. For example, in the manufacture of semiconductor chips such as microprocessors and other computer chips for example, a semiconductor wafer such as a silicon wafer is subjected to an ion implantation process, which introduces impurity atoms or dopants into a surface region of a device side of the wafer. The ion implantation process damages the crystal lattice structure of the surface region of the wafer, and leaves the implanted dopant atoms in interstitial sites where they are electrically inactive. In order to move the dopant atoms into substitutional sites in the lattice to render them electrically active, and to repair the damage to the crystal lattice structure that occurs during ion implantation, it is necessary to anneal the surface region of the device side of the wafer by heating it to a high temperature.
However, the high temperatures required to anneal the device side also tend to produce undesirable effects using existing technologies. For example, diffusion of the dopant atoms deeper into the silicon wafer tends to occur at much higher rates at high temperatures, with most of the diffusion occurring within close proximity to the high annealing temperature required to activate the dopants. As performance demands of semiconductor wafers increase and device sizes decrease, it is necessary to produce increasingly shallow and abruptly defined junctions, and therefore, diffusion depths that would have been considered negligible in the past or that are tolerable today will no longer be tolerable in the next few years or thereafter. Current industry roadmaps, such as; the International Technology Roadmap for Semiconductors 1999 Edition (publicly available at http://public.itrs.net/) indicate that doping and annealing technologies will have to produce junction depths as shallow as 30 nm by 2005, and as shallow as 20 nm by 2008.
Most existing annealing technologies are incapable of achieving such shallow junction depths. For example, one existing rapid thermal annealing method involves illuminating the device side of the wafer with an array of tungsten filament lamps in a reflective chamber, to heat the wafer at a high rate. However, the wafer tends to remain hot for a considerable time after the power supply to the tungsten filaments is shut off, for a number of reasons. Typical tungsten lamps have a relatively long time constant, such as 0.3 seconds, for example, as a result of the high thermal masses of the filaments, which remain hot and continue to irradiate the wafer after the power supply to the filaments is discontinued. This slow time response of the filaments gives rise to the dominant thermal lag in such a system. Also, radiation return from the walls of the reflective process chamber provides another source of continued heating after the power is shut off. A temperature versus time profile of the wafer using this tungsten lamp annealing method tends to have a rounded top with relatively slow cooling after the power to the filaments is discontinued. Accordingly, if the wafer is heated with such a system to a sufficiently high temperature to repair the crystal lattice structure and activate the dopants, the wafer tends to remain too hot for too long a period of time, resulting in diffusion of the dopants to significantly greater depths in the wafer than the maximum tolerable diffusion depths that will be required to produce 30 nm junction depths.
Although the vast majority of dopant diffusion occurs in the highest temperature range of the annealing cycle, lowering the annealing temperature is not a satisfactory solution to the diffusion problem, as lower annealing temperatures result in significantly less activation of the dopants and therefore higher sheet resistance of the wafer, which would exceed current and/or future tolerable sheet resistance limits for advanced processing devices.
One annealing method that has achieved some success in producing shallow junctions involves the use of excimer lasers to heat and anneal the device side of the wafer. The short-wavelength monochromatic radiation produced by such lasers tends to be absorbed at very shallow depths in the device side of the wafer, and the short duration, high-power laser pulse (for example, a 10 nanosecond pulse delivering about 0.4 J/cm
2
to the device side surface) typically used for this process tends to heat a small localized area of the surface of the device side to melting or near-melting temperatures very rapidly, in significantly less than the time required for thermal conduction in the wafer. Accordingly, the bulk regions of the substrate of the wafer tend to remain cold and therefore act as a heat sink for the heated surface region, causing the surface region to cool very quickly. A typical surface temperature versus time profile of the localized area of the device side surface using laser annealing tends to be triangular-shaped and steeply sloped for both the heating and cooling stages and therefore, the device side spends only a very short period of time at high temperatures. Thus, the wafer does not remain hot long enough for much dopant diffusion to occur. However, because the bulk regions of the wafer, as well as device side areas other than the localized area heated by the laser, remain cold when the localized surface area of the device side is heated to annealing temperature, extreme thermal gradients are produced in the wafer, resulting in large mechanical strains which cause the crystal planes within the wafer to slip, thereby damaging or breaking the crystal lattice. In this regard, a very small spatial movement may completely destroy the crystal lattice. Thermal gradients may also cause other damage, such as warpage or defect generation. Even in the absence of slippage, a non-uniform temperature distribution across the wafer may cause non-uniform performance-related characteristics, resulting in either inadequate performance of the particular wafer, or undesirable performance differences from wafer to wafer. In addition, the large amount of energy delivered by the laser or lasers to the device side of the wafer is non-uniformly absorbed by the pattern of devices thereon, resulting in deleterious heating effects in regions of the wafer where annealing is not desired, and may also produce further large temperature gradients causing additional damage to the silicon lattice.
Other ultra-fast heating methods similar to laser annealing have also been attempted. For example, flash lamps and microwave pulse generators have been used to rapidly heat the device side of the wafer to annealing temperature, resulting in a temperature-time profile similar to that achieved by laser annealing, with similar disadvantages.
At least one approach in the early 1990s involved a low-temperature annealing stage followed by a laser annealing stage. The low-temperature stage typically involved heating the wafer to a mid-range temperature in an electric furnace, such as 600° C. for example, for a relatively long period of time, such as an hour or longer. A typical temperature-time profile of the device side surface using this method is flat for a very long time, followed by a rapid increase and rapid cooling of the surface resulting from the laser anneal. Although this method purports to reduce junction leakage currents as compared to laser annealing alone, the long duration of the low-temperature annealing stage causes the dopants to diffuse to greater depths within the device side of the wafer. Such diffusion, which may have been tolerable or perhaps even negligible by early 1990s standards, would not permit the formation of sufficiently shallow junctions to comply with current performance and industry roadmap requirements.
A more recent approach involves the use of a fast responding argon plasma arc lamp heat source to irradiate the substrate side of th

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