Batteries: thermoelectric and photoelectric – Thermoelectric – Processes
Reexamination Certificate
2001-08-10
2004-04-27
Ryan, Patrick (Department: 1745)
Batteries: thermoelectric and photoelectric
Thermoelectric
Processes
C136S204000, C136S205000, C062S003200, C257S713000, C257S717000, C257S930000, C438S054000, C438S118000, C438S455000, C438S458000, C438S460000
Reexamination Certificate
active
06727422
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the field of heat sink and heat spreader structures and, more particularly, to heat sink/spreader structures which utilize thermoelectric effects to more efficiently dissipate thermal energy from heat sources including electronic devices and circuits.
DESCRIPTION OF THE RELATED ART
The performance levels of microelectronic devices (e.g., integrated circuits, power amplifiers) are continually increasing to keep pace with the demands of modern technology. Performance levels such as clock speed are closely tied to the number and density of features (e.g., transistors) patterned onto the microelectronic device. Faster processing by the microelectronic device demands faster clock speeds. Faster clock speeds, in turn, mean more switching and power dissipation per unit time.
Sub-micron transistors and other features are currently patterned onto silicon wafers with extremely high densities. For example, several million transistors can be patterned on a single square centimeter of silicon. Switching speeds as fast as a few nanoseconds can be achieved with each transistor.
In theory, the performance levels of microelectronic devices should continually improve as the size of the transistors is decreased and the density of the features is increased. In practice, however, small, closely packed features dissipate large amounts of heat which limit performance levels. Heat is often dissipated from small, select regions of the device typically by heat sinks.
Temperature control has thus emerged as the limiting factor in the design of microelectronic devices. New-age devices, such as high-power amplifiers and multi-chip modules, radiate particularly large amounts of heat. Failure to effectively conduct away heat leaves these devices at high operating temperatures, ultimately resulting in decreased performance and reliability.
Heat sinks are most efficient when there is a uniform heat flux applied over the entire base. “Spreading resistance” occurs when a heat sink with a large base-plate area is attached to a heat source of a smaller footprint area. This results in a higher local temperature at the location where the heat source is placed. The spreading resistance is directly influenced by the following variables:
Footprint or contact area of the heat source;
Footprint area of the heat sink base-plate;
Thickness of the heat sink base-plate;
Thermal conductivity of the heat sink base-plate;
Average heat sink thermal resistance;
Location of the heat source relative to the base-plate center point.
The typical approach to overcoming spreading resistance is to increase the size of the heat sink, increase the thickness of the base, increase the airflow across the heat sink, or decrease the incoming air temperature. These steps increase weight, noise, system complexity and expense. When a solution cannot be achieved, the impact can be lost profits due to reduced electronics' performance, decreased reliability due to high operating temperatures, increased fan speeds and delays in new product introductions while thermal issues are resolved.
To improve the thermal performance of an electronics or integrated circuit package, heat sinks and heat spreaders are added either internally or externally to the packages. However, the typical materials utilized exhibit a variety of shortcomings including: thermal expansion mismatch between the heat spreader and the chip, excessive weight, high cost and marginal thermal performance.
U.S. Pat. No. 5,229,327, granted to Farnworth on Jul. 20, 1993 discloses structures to cool semiconductor devices with Peltier junctions. Electric current is passed through the Peltier junctions and semiconductor device (both in series) via a heat sink acting as an electrical bus and mechanical support. In addition, layers of metal and semiconductor material are progressively layered upon a semiconductor die (over a passivated layer) and junctions formed to yield peltier cooling. Power to the Peltier junctions (positive and negative terminals) is provided through the semiconductor die.
U.S. Pat. No. 5,637,921, granted to Burward-Hoy on Jun. 10, 1997 relates to a cooled electronic component package in which a single or multistage thermoelectric device contacts an integrated circuit chip via a cold plate. The chip and thermoelectric device are located within a sealed component package cavity in order to cool the chip to sub-ambient temperatures without condensation.
U.S. Pat. No. 5,714,791, granted to Chi, et al. on Feb. 3, 1998 discloses a micromachined Peltier device in which a silicon substrate is doped from one face to yield thin P and N-type thermoelements on top of a thin silicon membrane. The cold junctions of the thermoelements are located above a cavity (aperture) to minimize thermal conduction through the silicon substrate.
U.S. Pat. No. 6,196,002, granted to Newman, et al. on Mar. 6, 2001 relates to a ball grid array (BGA) integrated circuit package containing a thermoelectric device cooling the IC chip. Power for the thermoelectric cooler is supplied by the BGA package via conductive contacts. The thermoelectric cooler is positioned partially within the package substrate and one face (which contacts the IC chip) is cooler than the opposite thermoelectric face.
U.S. Pat. No. 5,569,950, granted to Lewis, et al. on Oct. 29, 1996 relates to a device to monitor and control the temperature of IC chips with a thermoelectric cooler and thermocouple sensing. A thermocouple, placed between the chip and thermoelectric cooler, provides feedback to regulate power to the cooler.
U.S. Pat. No. 5,598,031, granted to Groover, et al. on Jan. 28, 1997 discloses an IC package whereby the IC chip is mounted to a separate silicon substrate (larger in surface area than chip) in order to provide heat spreading via thermal conduction. Additionally, electrical pads and circuit traces are disposed onto the substrate surface (over an oxide layer) in order to provide electrical connection between the IC chip and package.
U.S. Pat. No. 5,837,929, granted to Adelman on Nov. 17, 1998 discloses a thermoelectric device and fabrication method in which a doped semiconducting substrate contains oppositely doped regions thereby creating positive and negative type thermoelements. These vertically oriented thermoelements are electrically isolated by etching spaces and filling the spaces with a polyimide material.
U.S. Pat. No. 4,211,888, granted to Stein, et al. on Jul. 8, 1980 relates to a thermopile in a star-like pattern on top of a semiconductor substrate. One thermoelement type is formed by doping regions on the substrate and the dissimilar thermoelement type is a metal layer deposited over an oxide. The center junctions of the thermopile are heated by a source of thermal radiation to be measured.
U.S. Pat. No. 5,956,569, granted to Shiu, et al. on Sep. 21, 1999 relates to a thermoelectric cooler structure and fabrication method in which the cooler is formed on the backside of a semiconductor substrate. The thermoelements, perpendicularly oriented to the substrate, are fabricated by etching the substrate, depositing doped polysilicon layers, oxide insulating layers and metal contact layers.
U.S. Pat. No. 4,646,126, granted to Iizuka on Feb. 24, 1987 relates to a multiple IC chips mounted to a separate silicon substrate (via an oxide layer) and wiring layers interconnecting them.
U.S. Pat. Nos. 5,777,385 and 6,162,659, granted to Wu on Jul. 7, 1998 and Dec. 19, 2000 respectively disclose an electronic package structure in which a silicon heat spreader substrate is bonded to the backside to an IC chip via discrete, raised solder joints.
U.S. Pat. No. 5,032,897, granted to Mansuria, et al. on Jul. 16, 1991 discloses an integrated circuit package in which the IC chip is bonded to a thermoelectric cooler (thermoelements oriented perpendicular to the IC chip) and positioned within the package cavity.
U.S. Pat. No. 6,222,113, granted to Ghoshal on Apr. 24, 2001 relates to a thermoelectric cooler whose thermocouples are mounted to a doped semiconducting substra
Jensen & Puntigam P.S.
Parsons Thomas H.
Ryan Patrick
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