Heat dissipation from IC interconnects

Details Heat dissipation from IC interconnects Heat dissipation from IC interconnects

2003-05-16

2004-09-28

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S173000, C257S355000

Reexamination Certificate

active

06798066

ABSTRACT:

BACKGROUND OF INVENTION
Field of the Invention
The field of the present invention is semiconductor integrated circuits. More specifically, the present invention relates to dissipating heat in semiconductor integrated circuits.
Integrated circuits formed on a semiconductor substrate such as, for example, silicon, silicon-on-insulator (SOI), or silicon germanium (SiGe), include devices such as transistors, capacitors, resistors and inductors which are connected by interconnects (e.g. wires). Interconnects are typically located in Back-End-of-Line (BEOL) levels above the Front-End-of-Line (FEOL) devices of the integrated circuit. Interconnects and vias provide an electrical path between devices within an integrated circuit so that desired electrical connections are formed between devices. Interconnects can also provide electrical connection from devices to input/output pads for connection to an external signal (i.e. power supply, ground, or signal line). Since interconnects are used to provide electrical connection, interconnects are typically formed of an electrically conductive material such as, for example, a metal. Metals such as, for example, aluminum or copper are commonly used due to their relatively low electrical resistance.
Forming conductive interconnects and vias on a semiconductor substrate can be achieved by a variety of methods. For example, damascene and dual damascene processes can be used to form interconnects and vias. For a given wiring level, a dielectric layer is deposited, patterned and etched to form a trough for interconnects (i.e. damascene process) or interconnects and vias (i.e. dual damascene process). Metal is deposited to fill the trough and any metal overlying the dielectric layer is removed typically by a chemical mechanical polish (CMP). The dielectric layer electrically isolates interconnects from each other. In addition, as heat is generated due to electrical current flowing through an interconnect, the dielectric layer provides a thermal conduction path so that heat can be dissipated away from the interconnect.
In order to increase the speed of integrated circuits, the size of devices and interconnects that form integrated circuits must be reduced. Two effects limiting the speed of integrated circuits are the electrical resistance of the interconnect (i.e. line resistance) and resistive-capacitive (RC) coupling induced time delay due to higher wiring density and closer spacing of interconnects. As the distance between adjacent interconnects decreases, RC coupling between adjacent interconnects increases. To reduce line resistance, aluminum interconnects are being replaced with copper interconnects since copper has a lower electrical resistance than aluminum. RC coupling induced time delay is being addressed by the use of low dielectric constant (low-k) dielectrics such as, for example, polyimide nanofoams (also known by tradenames such as, for example, SiLK which is manufactured by Dow Chemical Co., Midland, Mich.), to replace conventional dielectrics (i.e. silicon oxide). By utilizing a low-k dielectric, the capacitance between adjacent interconnects is reduced, thus reducing the RC coupling induced time delay.
Due to lower electrical interconnect resistance and lower RC coupling induced time delay afforded by the use of copper interconnects and low-k dielectrics, increased current flow can be applied to the interconnects in order to provide higher performance integrated circuits (i.e. higher operating frequency). Also, interconnects are exposed to undesirable current flow such as high current, short time duration pulses caused by, for example, an electrostatic discharge (ESD) event or a power up/down event. High current flow through an interconnect results in the generation of a large amount of heat which must be effectively dissipated.
The combination of copper interconnects with a low-k dielectric creates a thermal dissipation problem in an integrated circuit. Low-k dielectrics characteristically do not provide heat dissipation as well as silicon oxide dielectrics. Additionally, some low-k dielectrics, especially types formed of organic foams, will degrade both structurally and electrically at temperatures exceeding about 350° C. If heat is not adequately dissipated from the interconnect, the temperature of the interconnect increases and the electrical resistance of the interconnect also increases, thus degrading the performance of the integrated circuit. If enough heat is generated, the interconnect can melt leading to reliability issues and/or failure of the interconnect. The migration of interconnects from aluminum to copper has improved the thermal robustness of interconnects since the melting temperature of copper is higher than aluminum. However, continued scaling of copper interconnects to smaller dimensions to meet increased integrated circuit requirements will expose copper interconnects to temperatures that exceed the melting temperature of copper.
Dissipating heat from an interconnect formed in a low thermal conductivity dielectric is desired.
SUMMARY OF INVENTION
It is thus an object of the present invention to dissipate heat from an interconnect formed in a low thermal conductivity dielectric.
The foregoing and other objects of the invention are realized, in a first aspect, by an integrated circuit apparatus including integrated circuit devices interconnected by conductive interconnection metallurgy and input/output pads subject to electrostatic discharge events. At least one latent heat of transformation absorber is associated with at least one of the input/output pads for preventing the energy generated by an electrostatic discharge event from damaging the conductive interconnection metallurgy.


REFERENCES:
patent: 5623387 (1997-04-01), Li et al.
patent: 6259139 (2001-07-01), Pan

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