Heak sink chip package

Details Heak sink chip package Heak sink chip package

2002-05-16

2003-05-13

Chervinsky, Boris (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S707000, C361S709000, C361S717000, C361S760000, C257S706000, C257S707000, C165S080200, C165S185000

Reexamination Certificate

active

06563712

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to a microelectronic assembly. More particularly, the present invention relates to heat management for packaged microelectronic assemblies. In particular, the present invention relates to a solder structure that acts as a heat sink for generated heat management and for resistance to destructive mechanical stresses experienced in packaged microelectronic devices.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
In the packaging of microelectronic devices, heat management and mechanical stress management are important aspects of producing a reliable microelectronic article. The heat sink of a chip package allows for enhanced performance of the microelectronics. As the heat sink is bonded to supporting structures, disparate amounts of mechanical expansion between the supporting structures, the chip itself, and the printed circuit board (PCB) cause mechanical stresses that may cause the chip packaging process to have a low yield or that may cause the chip package to come apart during field use. As chips are being frequently packaged in connection with a PCB that has a ball array, mechanical stresses experienced in the chip package are transferred through individual solder balls in the ball array.
Miniaturization is the process of crowding an increasing number of microelectronic circuits onto a single chip. Additionally, miniaturization involves the reduction of the overall chip package size so as to achieve smaller and more compact devices such as hand-held computers, personal data assistants (PDA), portable telecommunication devices, and the like. Ideally, the chip package size would be no larger than the chip itself.
As the overall package is subject to miniaturization, ball arrays have been reduced to less than 1 mm pitch. Miniaturization has the counter-productive effect upon chip packaging of an increased heat load but a smaller chip package structure available to extract heat from the chip package.
FIG. 1
is a prior art depiction of a microelectronic chip package
10
that includes an integrated circuit chip
12
. Bonded to integrated circuit chip
12
is a heat sink
15
that may be made of a material such as copper or some other metal having a preferred coefficient of thermal conductivity. A chip carrier
16
is bonded
30
to heat sink
15
. A ball array
18
makes connection between chip carrier
16
and a printed circuit board
20
.
Chip package
10
has a geometric center
22
that is considered to be the center of mechanical expansion and contraction. By “geometric center” it is understood that an integrated circuit chip may heat substantially uniformly or nonuniformly, depending upon what portions of the chip are most active during any given use. Thus the “geometric center” is understood to be the center of mechanical expansion for a given chip; the chip being the primary source of generated heat. The geometric center of a chip package may thus be considered to be the chip itself or, when viewed more closely, it may be considered to be the bilaterally symmetrical center region of the chip when observed in either cross section or plan view.
Ball arrays
18
may comprise an outer ball row
24
and an inner ball row
26
. As chip package
10
expands and contracts during ordinary usage, although expansion and contraction at geometric center
22
is substantially nonexistent, mechanical stress experienced in ball arrays
18
becomes greater farther away from geometric center
22
. In other words, outer ball row
24
experiences greater mechanical stress than inner ball row
26
. Because outer ball row
24
is more susceptible to shear induced by mechanical effects than inner ball row
26
, eventually, electrical contact is compromised and a yield failure during burn in occurs, or a field failure occurs.
As it is desirable to miniaturize a chip package, it is also notable within chip package
10
that heat sink
15
provides structure that causes the overall size of chip package to have an enhanced profile when viewed in elevational cross-section. This enhanced profile is counter to miniaturization. Thus, conflicting objectives and constraints exist between overall package size and heat management that will prevent destructive mechanical stress.
What is needed in the art is mechanical shear minimization of chip packaging that overcomes the problems of the prior art.
SUMMARY OF THE INVENTION
The present invention relates to the use of a heat sink in the form of a dummy solder ring or dam structure to be part of a microelectronic chip package. The present invention is particularly useful for board on chip (BOC) packages on a mother board, memory modules, or the like. The present invention is also particularly useful for chip on board (COB) packages. Additionally, the present invention is useful for flip chip on board technology, and ball grid arrays (BGAs) and other chip scale packages.
In the present invention a solder ring or dam heat sink is disposed upon a printed circuit board (PCB), upon the same side as the ball array, and in a manner that encircles or externally borders the ball array. Because the chip package is in close quarters with several heat-generating devices, and because they are usually housed in an enclosure such as a computer case, the chip package environment is at elevated temperatures. The elevated temperatures often require assisted cooling such as with a blower. At the elevated temperatures, the entire chip package becomes heated such that expansion and its accompanying mechanical stress is experienced. As a result, the largest proportion of mechanical stress is transferred through the solder ring or dam heat sink at the periphery of the chip package instead of through the individual balls of the ball array.
In a BOC embodiment of the present invention the integrated circuit chip is disposed upon the PCB underside, the active surface thereof is mounted on the PCB underside, and the integrated circuit chip is wire bonded to the PCB upper side. The PCB has a slot through which wire bonding connects the PCB traces to the integrated circuit chip.
In another embodiment of the present invention, the BOC technology is configured with the ball arrays upon the PCB upper side along with the solder ring or dam heat sink encircling and/or bordering the ball array, and additionally a chip-opposite heat sink may be attached to the PCB underside. With the additional chip-opposite heat sink, thermal management of the chip package is enhanced.
In another alternative embodiment of the present invention, COB technology includes the integrated circuit chip in which, the ball array, and the solder ring or dam heat sink are located upon the PCB underside. Additionally, a chip-level heat sink may be placed on the PCB upper side for enhanced thermal management qualities.
In another alternative embodiment, a flip chip has its ball array encircled or bordered by a solder ring or dam heat sink respectively. The heat sink is either directly bonded to the active surface of the flip chip, or to a die attach.
In another embodiment, a stack of chip packages is provided. In another embodiment, at least two chips are contacted by a PCB. In another embodiment, a stack of PCB is provided, wherein each PCB has at least two chips disposed on one side thereof.
These and other features of the present invention will become more fully apparent

Affiliated with

Also associated with

Rating

Heak sink chip package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Heak sink chip package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Heak sink chip package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3081468