Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-08-09
2002-07-23
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S691000, C438S692000
Reexamination Certificate
active
06423640
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a planarization process for a semiconductor material deposited on a semi-conducting substrate and more particularly, relates to a headless chemical mechanical polishing process for planarizing an oxide layer on a semi-conducting substrate without using a polishing disc and a polishing head and an apparatus for conducting the process.
BACKGROUND OF THE INVENTION
Apparatus for polishing thin, flat semi-conductor wafers is well-known in the art. Such apparatus normally includes a polishing head which carries a membrane for engaging and forcing a semiconductor wafer against a wetted polishing surface, such as a polishing pad. Either the pad, or the polishing head is rotated and oscillates the wafer over the polishing surface. The polishing head is forced downwardly onto the polishing surface by a pressurized air system or, similar arrangement. The downward force pressing the polishing head against the polishing surface can be adjusted as desired. The polishing head is typically mounted on an elongated pivoting carrier arm, which can move the pressure head between several operative positions. In one operative position, the carrier arm positions a wafer mounted on the pressure head in contact with the polishing pad. In order to remove the wafer from contact with the polishing surface, the carrier arm is first pivoted upwardly to lift the pressure head and wafer from the polishing surface. The carrier arm is then pivoted laterally to move the pressure head and wafer carried by the pressure head to an auxiliary wafer processing station. The auxiliary processing station may include, for example, a station for cleaning the wafer and/or polishing head; a wafer unload station or, a wafer load station.
More recently, chemical-mechanical polishing (CMP) apparatus has been employed in combination with a pneumatically actuated polishing head. CMP apparatus is used primarily for polishing the front face or device side of a semiconductor wafer during the fabrication of semiconductor devices on the wafer. A wafer is “planarized” or smoothed one or more times during a fabrication process in order for the top surface of the wafer to be as flat as possible. A wafer is polished by being placed on a carrier and pressed face down onto a polishing pad covered with a slurry of colloidal silica or alumina in de-ionized water.
A schematic of typical CMP apparatus is shown in
FIGS. 1A and 1B
. The apparatus for chemical mechanical polishing consists of a rotating wafer holder
14
that holds the wafer
10
, the appropriate slurry
24
, and a polishing pad
12
which is normally mounted to a rotating table
26
by adhesive means. The polishing pad
12
is applied to the wafer surface
22
at a specific pressure. The chemical mechanical polishing method can be used to provide a planar surface on dielectric layers, on deep and shallow trenches that are filled with polysilicon or oxide, and on various metal films. CMP polishing results from a combination of chemical and mechanical effects. A possible mechanism for the CMP process involves the formation of a chemically altered layer at the surface of the material being polished. The layer is mechanically removed from the underlying bulk material. An altered layer is then regrown on the surface while the process is repeated again. For instance, in metal polishing a metal oxide may be formed and removed repeatedly.
In the CMP process, large raised features and large recessed areas polish at about the same rate as the background area, or as a blanket film. The normal high polish rate of raised features and non-polishing of depressions is therefore not seen in these cases due to the flexibility of the polishing pad and to some extent, the polishing head. A planarization by just polishing is therefore difficult to achieve.
It has also been observed that clusters of closely spaced narrow features act as a large feature and is polished at a corresponding slower polishing rate. This further works against achieving global planarization. The various polishing defects that have been observed include non-uniformity, rounding, dishing and erosion. The dishing and erosion defects are shown in
FIGS. 2A and 2B
where the original surfaces before polishing are indicated by the dotted lines. To some extent, the severity of these polishing defects can be reduced by modifications made in the CMP process. For instance, the pad/slurry parameters may be adjusted by using a harder pad which polishes recessed areas more slowly than soft pads. Another approach that has been tried is to reduce the variation in pattern density. However, this is hard to implement since it involves changing the chip layout and circuit design.
In recent years, copper dual damascene process has become a popular method to form back-end-of-line interconnects. However, dishing and erosion defects are frequently encountered in the copper CMP process which is part of the damascene process in an undesirable topography of post-oxide deposition. The existence of topography recess causes the existence of metal residues which may either short the metal interconnects or impact the reliability of the device built.
Typical dishing and erosion defects occurring in a copper CMP process are shown in
FIGS. 3A and 3B
. As shown in
FIG. 3B
, metal residues
30
of either copper or TaN (a liner material) is left after the CMP process is completed which causes a short between the metal interconnects
28
. The metal residues
30
is formed by the existence of a recess in the topography of the oxide (inter-metal-dielectric or IMD) layer
32
. The exact location of the metal residues
30
determines the possible occurrence of a functional failure or a reliability problem. The topographic oxide recess is produced inherent from the dishing and/or erosion of copper CMP and the conformal oxide deposition of layer
32
. Presently, the only possible solution is to improve the copper CMP recipe, and thus the copper CMP planarization process, to alleviate the dishing and/or the erosion problem. However, based on the inherent characteristics of the copper CMP process, it is difficult and costly to completely eliminate the dishing and erosion defect. it is therefore an object of the present invention to provide a method for oxide planarization that does not have the drawbacks or shortcomings of the conventional CMP method.
It is another object of the present invention to provide a method for oxide planarization by using a headless and padless spin etching process.
It is a further object of the present invention to provide a headless and padless chemical mechanical polishing process for oxide planarization by a spin etching.
It is another further object of the present invention to provide a padless and headless CMP process for oxide planarization by injecting a solvent/abrasive particles mixture onto an oxide surface.
It is still another object of the present invention to provide a headless and padless CMP process for oxide planarization by loading abrasive particles in a solvent for oxide and injecting the mixture onto the oxide surface.
It is yet another object of the present invention to provide a headless and padless CMP process for oxide planarization that is capable of substantially eliminating the dishing and erosion defects.
It is still another further object of the present invention to provide an apparatus for planarizing an outside surface on a semi-conductor wafer which includes a wafer platform capable of rotating at a speed of at least 1000 RPM and a solvent/abrasive particles mixture dispensing unit for injecting the mixture onto the oxide surface.
It is yet another further object of the present invention to provide an apparatus for planarizing an oxide surface on a semiconductor wafer that is capable of mixing and injecting an aluminum oxide particle loaded diluted HF solution onto an oxide surface on a wafer that is rotated at a speed of at least 1000 RPM.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for planarizing an oxide su
Lee Tze-Liang
Yang Fan-Keng
Yu Chen-Hwa
Deo Duy-Vu
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung Randy W.
Utech Benjamin L.
LandOfFree
Headless CMP process for oxide planarization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Headless CMP process for oxide planarization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Headless CMP process for oxide planarization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2903742