Dynamic magnetic information storage or retrieval – Automatic control of a recorder mechanism – Controlling the head
Patent
1988-09-27
1991-06-18
Psitos, Aristotelis M.
Dynamic magnetic information storage or retrieval
Automatic control of a recorder mechanism
Controlling the head
369 32, G11B 555, G11B 2108
Patent
active
050253301
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a head positioning control system for a memory device, more specifically relates to a head positioning control system which is provided at the drive control unit of a memory device, which attempts to reduce the control processing load of a control circuit for positioning the head at a target position of a memory medium, and which enables the control circuit to maintain control tracking at a high precision even with respect to higher densities of the memory medium and high speed movement of the head.
2. Description of the Related Art
One example of a memory device in which head positioning is performed, is the magnetic disk apparatus shown in FIG. 1. In FIG. 1, there are shown a magnetic disk control unit 1 connected to a main computer (not shown), a magnetic disk drive control unit 2', a servo head 4 for reading servo information from one magnetic disk, among the magnetic disks, on which the servo information is recorded, and a voice coil motor 9 which moves the servo head 4 and other magnetic heads (not shown) to a target cylinder. FIG. 1 also shows a position signal generation system 5' which issues a cylinder (track) position signal based on servo information from the servo head 4, a speed control system 6 which performs speed control on the servo head 4 to position the servo head at the target cylinder (track) in the coarse control mode, and a position control system 7 which performs fine position control of the servo head 4 to the target cylinder in a fine control mode after the completion of the speed control.
The magnetic disk control unit 1 is provided so as to perform buffered processing to enable access to the magnetic disk apparatus without the main computer (not shown), provided as a host, being affected by the operation of the magnetic disk drive control unit 2' and the magnetic disk drive unit 1.
The magnetic disk drive control unit 2' has, mutually connected via a bus 30, the following: an interface (I/F) unit 21, a microprocessor unit (MPU) 22', a random access memory (RAM) 23' which stores control data, etc., a read only memory (ROM) 24 in which programs for operating the MPU 22' and other control patterns are stored, a timer 25, a ROM 26 which stores the speed control reference table, a digital-analog converter (DAC) 27 which outputs the reference speed Vr as an analog amount, an output register 28' which outputs a mode signal indicating to a multiplexer 81 either the coarse mode or fine mode, an input register 29 which receives as input a track cross pulse TRXP' output from the position signal generation system 5' each time the head cuts across the cylinder, and an analog-digital converter (ADC) 31 which converts the current head position POS to a digital amount.
The position signal generation system 5' has a servo signal amplification circuit 51 which amplifies the servo signal from the servo head 4, a position signal generation circuit 52, a position information generation circuit 53, a track cross pulse generation circuit 54', a wave shaper circuit 55', and a signal change circuit 56. The details of each of these will be given later.
The speed control system 6 has, for providing a reference speed Vr, reference speed table ROM 26, MPU 22', and digital-analog converter (DAC) 27 and, for providing an actual speed Va, circuits 51 to 53 and 56 in the position signal generation system 5', differential circuit 63 for differentiating the position signal POS output from the signal change circuit 56 and outputting an original speed signal Va', a control current detection circuit 83 of the current corresponding to VCM 9 for issuing a feedback signal for correcting the original speed signal Va', and a speed signal generation circuit 61 for receiving as an input the original speed signal Va' and the feedback signal from the control current detection circuit 83 and outputting a corrected speed signal Va. The speed control system 6 further has a speed deviation calculation circuit 62 which outputs the difference
REFERENCES:
patent: 4068269 (1978-01-01), Commander et al.
Fujitsu Limited
Garland Steven R.
Psitos Aristotelis M.
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