Head of line blockage avoidance system and method of...

Details Head of line blockage avoidance system and method of... Head of line blockage avoidance system and method of...

2002-01-09

2008-09-09

Backer, Firmin (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S236000, C370S413000

Reexamination Certificate

active

07424027

ABSTRACT:
A head of line blockage avoidance system for use with network systems that employ packets having an associated priority and a method of operation thereof. In one embodiment, the head of line blockage avoidance system includes: (1) m inputs, m numbering at least two, configured to receive the packets, (2) n packet first-in-first-out buffers (FIFOs), n numbering at least three, each of the packet FIFOs configured to receive at least one of the packets from the m inputs, (3) a priority summarizer configured to generate a priority summary of the packets within the m inputs and the n packet FIFOs, and (4) a scheduler configured to cause one of the n packet FIFOs to be queued for processing based on the priority summary.

REFERENCES:
patent: 5539729 (1996-07-01), Bodnar
patent: 6667983 (2003-12-01), Lo et al.
patent: 6912225 (2005-06-01), Kohzuki et al.
patent: 6938097 (2005-08-01), Vincent et al.
patent: 6963576 (2005-11-01), Lee
patent: 2001/0050916 (2001-12-01), Krishna et al.
patent: 2002/0085578 (2002-07-01), Dell et al.

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