HDTV trellis decoder architecture

Details HDTV trellis decoder architecture HDTV trellis decoder architecture

2007-10-30

2007-10-30

Payne, David C. (Department: 2611)

Pulse or digital communications

Systems using alternating or pulsating current

Plural channels for transmission of a single pulse train

C375S316000, C375S340000, C375S341000

Reexamination Certificate

active

10511398

ABSTRACT:
A trellis decoding system for use in processing a High Definition Television signal. The trellis decoding system includes a traceback unit that identifies a sequence of antecedent trellis states in accordance with a state transition trellis. A branch metric computer includes eight discrete subunits, one for each possible trellis state. Each subunit generates two output bits indicative of the two trellis branches exiting the trellis state represented by that particular subunit. An add-compare-select unit includes eight discrete subunits, each associated with a particular trellis state. Each subunit includes as an input two bits received from the branch metric computer and as an output two bits. Bit31is chosen from28and29. Bit6is chosen from the branch metric information input to each subunit. A traceback control memory unit includes an N to 1 multiplexer which receives as an input the output bits from the add-compare-select unit. The present system offers a hardware reduction from prior art.

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William W. Lin et al. “A Trellis Decoder for HDTV”, Samoff Corporation US, Aug. 1999, IEEE Transactions on Consumer Electronics, vol. 45, No. 3, pp. 571-576.
Search Report Dated Jul. 27, 2003.

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