HDTV decoder

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358135, 341 67, H04N 713

Patent

active

052803490

ABSTRACT:
An HDTV decoder comprises a variable length decoder for decoding variable length code words in parallel to generate fixed length code words. A buffer for buffering the fixed length code words is connected to an output of the variable length decoder. A run length decoder is connected to an output of the buffer for run length decoding the fixed length code words. The variable length decoder has the same input and output running speed, which running speed is larger than an average speed and smaller than a burst speed at which said parallel variable length decoder would have to operate in the absence of said buffer. When the variable length decoder is capable of decoding more than one variable length code word in a cycle, the required buffer is quite small. It may be less than 1 k byte and may be on the order of 100 bytes. In this case, the variable length decoder and buffer may be incorporated in a single integrated circuit.

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