HDLC hardware accelerator

Details HDLC hardware accelerator HDLC hardware accelerator

2006-05-10

2009-10-20

Trost, IV, William (Department: 2416)

Multiplex communications

Communication techniques for information carried in plural...

Byte assembly and formatting

C370S470000, C370S472000, C370S522000, C714S757000, C714S758000, C714S776000, C714S781000, C714S807000

Reexamination Certificate

active

07606266

ABSTRACT:
An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

REFERENCES:
patent: 4703478 (1987-10-01), Haselton et al.
patent: 5325372 (1994-06-01), Ish-Shalom
patent: 5571718 (1996-11-01), Yip et al.
patent: 5638370 (1997-06-01), Seconi et al.
patent: 5671223 (1997-09-01), Shacher et al.
patent: 5671237 (1997-09-01), Zook
patent: 5724368 (1998-03-01), Zook
patent: 5978386 (1999-11-01), Hamalainen et al.
patent: 6212660 (2001-04-01), Joeressen et al.
patent: 6249525 (2001-06-01), Aggrawal et al.
patent: 6295626 (2001-09-01), Nair et al.
patent: 6493766 (2002-12-01), Buchholz et al.
patent: 6788652 (2004-09-01), Hwang
patent: 6836869 (2004-12-01), Wyland
patent: 6982963 (2006-01-01), Asahina
patent: 7009978 (2006-03-01), Kofoed et al.
patent: 7096261 (2006-08-01), Abrol et al.
patent: 2002/0144208 (2002-10-01), Gallezot et al.
patent: 0444832 (1991-09-01), None
patent: 0602806 (1994-06-01), None
patent: 02073910 (2002-09-01), None
W. Simpson, “PPP in HDLC-Like Framing,” Network Working Group, Jul. 1994, pp. 1-24.
Roginsky, Allen L., et al.: “Efficient Computation of Packet CRC From Partial CRCs With Application To The Cells-In-Frames Protocol;” Computer Communications, Elsevier Science Publishers BV, Amsterdam, NL, vol. 21, No. 7, Jun. 15, 1998, pp. 654-661, XP004132233.

Affiliated with

Also associated with

Rating

HDLC hardware accelerator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with HDLC hardware accelerator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and HDLC hardware accelerator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4053063