HDD chip set partitioning

Details HDD chip set partitioning HDD chip set partitioning

1997-12-19

2001-01-02

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting, per se, of an ac input to corresponding dc at an...

C360S075000

Utility Patent

active

06169429

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to read channel circuits, and more particularly to the chips that the read channel circuits are formed on.
BACKGROUND OF THE INVENTION
The total number of chips required to implement a hard disk drive system varies but may be 7 chips. These chips may be titled read-channel, servo, preamp, DRAM, Controller, flash memory, DSP. Consolidating the digital CMOS chips together in a single chip (or any form of combination of these chips) allows reduction of total number of chips needed and offers lower cost.
This is shown in FIG.
1
and allows for the DSP, the controller and possibly DRAM and Flash memory in a single chip.
Chip consolidation allows improved performance at the right time with lowest cost.
In order to reduce development time of read-channel circuits and improve testability, the read-channel has been designed digitally. However, this digital design requires a conversion of the necessary signals from analog-to-digital in a forward section of the communication channel (read-channel). However, no matter how soon or how far forward the signal processing becomes digital in the read-channel, the analog front-end remains to be the most critical in terms of development time and performance delivery. As integration in a digital CMOS process is required to achieve cost, time and performance, the analog front-end becomes harder and trickier to implement. Advanced CMOS processes with small feature size require lower supply voltage which will affect the performance of the analog front-end significantly, lower signal-to-noise, lower supply rejection and longer design cycle. Moreover, typical generic CMOS process does not contain capacitors, resistors nor low-threshold devices that are necessary to achieve improved analog performance at lower area. Incorporating any of these electrical elements in a generic CMOS process is generally non-standard and will result in higher cost, longer process development and untransportable design. Therefore the analog front-end in the read channel is one of the most important problems to allow full integration of chip sets. The integration, is affected by higher digital noise, higher noise coupling via substrate, lower data rate, lower supply rejection (no cascade at low supply), and higher process fluctuation.
This integration does not necessarily mean low-cost because the capacitor area is large (Metal/Metal cap), and low performance, i.e. analog front-end will require digital equalization (larger number of taps) to fix the non idealities.
SUMMARY OF THE INVENTION
A new architectural partitioning for chip integration is proposed that allows for low-cost while delivers performance at a much lower risk than previous proposal.


REFERENCES:
patent: 4783705 (1988-11-01), Moon et al.
patent: 5396384 (1995-03-01), Caldeira et al.
patent: 5493454 (1996-02-01), Ziperovich et al.
patent: 5544135 (1996-08-01), Akin, Jr et al.
patent: 5668679 (1997-09-01), Swearingen et al.
patent: 5844426 (1998-12-01), Sheahan et al.
patent: 5852524 (1998-12-01), Glover et al.
patent: 5854714 (1998-12-01), Reed et al.
patent: 5854717 (1998-12-01), Minuhin

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