Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2002-10-04
2004-07-20
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S588000
Reexamination Certificate
active
06765243
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to fabrication of HBT semiconductor devices.
2. Background Art
In a heterojunction bipolar transistor, or HBT, a thin silicon-germanium (“SiGe”) layer is grown as the base of a bipolar transistor on a silicon wafer. The SiGe HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Speed and frequency response can be compared by the cutoff frequency which, simply stated, is the frequency where the gain of a transistor is considerably reduced. Cutoff frequencies in excess of 100 GHz have been achieved for the HBT, which are comparable to the more expensive GaAs. Previously, silicon-only devices have not been competitive for use where very high speed and frequency response are required. The higher gain, speed and frequency response of the SiGe HBT are possible due to certain advantages of silicon-germanium, such as a narrower band gap and reduced resistivity. These advantages make silicon-germanium devices more competitive than silicon-only devices in areas of technology where high speed and high frequency response are required.
The advantages of high speed and high frequency response discussed above require, among other things, that certain dimensions, such as the width of an emitter structure in a self-aligned HBT, be very accurately controlled. The emitter width is a dimension that critically affects the performance of HBTs, and is considered a critical dimension, or “CD.” A polycrystalline silicon emitter can be formed on the surface of a single crystal silicon-germanium base by several methods. For example, one method is to form a layer of some material which can be selectively etched to the single crystal silicon-germanium base to open a “window” in that material in which to deposit the polycrystalline silicon for the emitter. Thus, dimensional control of the emitter window opening is crucial in the formation of the emitter structure. Moreover, as device feature sizes become smaller, it becomes more difficult to accurately control the dimensions of features such as an emitter window opening. Conventional methods for creating the emitter window opening have proven less than satisfactory.
Control of feature dimensions of a silicon-germanium HBT is difficult because every step in the photolithographic patterning process contributes variations. For example, unwanted variation in dimension of a feature may be caused by defects in the photomask; reflectivity of a surface of the material below the photoresist, referred to as “subsurface reflectivity”; adhesion problems between an antireflective coating and the wafer and photomask; or poor matching of index of refraction between an antireflective coating and the photomask. Thus, as feature sizes become smaller, the CD budget becomes stricter, necessitating more accurate control over critical dimensions such as the width of the emitter window opening in a SiGe HBT. In the case of the SiGe NPN HBT, for example, control of the emitter window opening width is essential to the performance of the device.
Previous approaches to provide a practical, reliable method for accurately controlling feature dimensions of a silicon-germanium HBT, such as the formation of an emitter window opening, have met with various difficulties. For example, in one approach utilizing a double polysilicon process, an emitter window opening is formed in a SiO
2
/poly stack. The double polysilicon process, however, is not compatible with SiGe technology. Another approach utilizing a selective epitaxy process results in poor manufacturing yield due to difficulties in controlling the selective epitaxy process. In yet another approach, a high-pressure oxide process has been utilized to provide accurate control of feature dimensions of a silicon-germanium HBT. However, the high-pressure oxide process requires specialized equipment and is not amenable to volume CMOS production.
A further approach to providing accurate control over feature dimensions of a silicon-germanium HBT utilizes a silicon oxide layer deposited over a sacrificial polysilicon emitter, which is situated between silicon oxide spacers. In the above approach, the silicon oxide layer and the sacificial polysilicon emitter are patterned and etched to form an emitter window opening between the silicon oxide spacers. However, in the above approach, manufacturing control of the resulting emitter window opening has been poor due to the photolithographic and etch properties of the silicon oxide layer.
Thus, there is a need in the art for accurate dimensional control of an emitter window opening in an HBT.
SUMMARY OF THE INVENTION
The present invention is directed to method for controlling an emitter window opening in an HBT and related structure. The present invention addresses and resolves the need in the art for accurate dimensional control of an emitter window opening in an HBT.
According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor, for example, may be an NPN silicon-germanium heterojunction bipolar transistor. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The first and second spacers, for example, may be silicon oxide. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. For example, the intermediate oxide layer may be silicon oxide and may have a thickness of approximately 300.0 to 1000.0 Angstroms.
According to this exemplary embodiment, the heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The amorphous layer may be, for example, amorphous silicon. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The antireflective coating layer may be, for example, an inorganic material such as silicon oxynitride.
According to this exemplary embodiment, the heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer. The heterojunction bipolar transistor may further comprise an emitter situated in the emitter window opening. The emitter, for example, may be a polycrystalline material, such as polycrystalline silicon. In another embodiment, the present invention is a method that achieves the above-described heterojunction bipolar transistor. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
REFERENCES:
patent: 5581114 (1996-12-01), Bashir et al.
patent: 6482710 (2002-11-01), Oda et al.
Kalburge Amol M.
Schuegraf Klaus F.
Yin Kevin Q.
Farjami & Farjami LLP
Jackson Jerome
Newport Fab LLC
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