HBr silicon etching process

Details HBr silicon etching process HBr silicon etching process

2000-05-26

2002-03-19

Utech, Benjamin L. (Department: 1746)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S714000, C438S719000

Reexamination Certificate

active

06358859

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes related to the formation of STI (shallow trench isolation).
(2) Background to the Invention and Description of Related Art
The formation of integrated circuit devices on silicon substrates requires that a means be provided to electrically isolate the various circuit components from each other. To this end regions of field insulation, typically of silicon oxide, are formed adjacent to the circuit components.
The well known method of local oxidation of silicon(LOCOS) to form field oxide isolation around semiconductive devices built into the surface of silicon wafers has been practiced for over twenty-five years and has served well to provide field isolation for many applications. Over the years many problems with LOCOS have surfaced which have been addressed in a great variety of ways. Most notable are the problems which deal with the growth of oxide under the hardmask used to define the oxide regions and the resultant uneven surface topology over the field oxide. The oxide penetration under the mask is commonly referred to as birds-beak. These problems still persist and become aggravated as the technology tends towards smaller, shallower devices at high densities.
A promising replacement for LOCOS field oxide isolation has been found in trench isolation. Although deep trench isolation(DTI) has been used nearly as long as LOCOS for bipolar transistor isolation, it has not been widely practiced in the manufacture of CMOS (complimentary metal oxide silicon) integrated circuits. More recently, however, as device densities increase and isolation widths become smaller, shallow trench isolation(STI) is gaining favor over LOCOS in CMOS technology. The Trenches are formed in the silicon around the semiconductor devices by reactive ion etching. They are then lined with a thin thermal silicon oxide and filled with silicon oxide or with another material such as polysilicon. Although a number of halogen chemistries have been reported for etching the silicon trenches, one of the most successful and widely preferred contains HBr as the primary etchant.
Wong, et.al., U.S. Pat. No. 5,874,362 reports the etching of high aspect ratio (depth/width) silicon and polysilicon trenches with the brominate gases HBr and CF
2
Br
2
and with the iodinate gas Hl. Grimard, et.al., U.S. Pat. No. 5,605,603 reports comparable results of 8-12 micron deep silicon trenches with desirable profiles and low mask erosion using an etchant containing HBr and NF
3
. The use of this etchant combination results in improved high aspect ratio trench profiles.
A problem with reactive etching with HBr is that bromine can become strongly chemisorbed onto surfaces of the wafer, presumably in the form of Si—O—Br segments which occurs as a by-product of trench etching. Also bromine is chemisorbed onto the surface of a silicon oxide hardmask, which is typically used for etching STI trenches. In addition bromine adsorbs directly onto the freshly exposed silicon surfaces. On a 200 or 300 mm diameter wafer, the chemisorbed bromine is spread over a considerable amount of surface area. The bromine thus adsorbed cannot be pumped or flushed out in the conventional manner after the etching process is completed. As a result, when the wafer is subsequently exposed to atmospheric moisture the bromine is liberated as HBr according to the reaction:
H
2
O+Si—O—Br→HBr+SiO
2
Most present day etching tools are of the single wafer variety which employ a load lock through which wafers are loaded and unloaded to the main etching chamber. It is in the load lock chamber, that the wafer becomes exposed to moisture. The liberated HBr causes corrosion of metal surfaces in the load lock chamber which is accompanied by the formation of particulates. These particulates subsequently find their way onto wafer surfaces causing yield loss. In addition the reaction causes the formation of SiO
2
particulates which also contribute to yield loss. While the main etching chamber is relatively well protected from atmospheric moisture, the residual HBr acts primarily within the load lock chamber.
Aside from wafer yield losses, the liberation of HBr from wafer surfaces also becomes a safety hazard. Whereas a level of less than 3 ppm of HBr may be considered to be a safe level of HBr, measurements made by the present inventors have shown HBr levels of about 9 ppm in the neighborhood of the etching tool when operated in the conventional manner.
It is therefore desirable to have a procedure for removing all residual bromine, including that which is chemisorbed on the wafer before the wafer is exposed to atmospheric moisture. In addition, in a high throughput manufacturing operation, it is sought to effect such removal with dispatch without requiring extensive pumping or baking to dislodge the chemisorbed bromine. The process disclosed by this invention is such a method.
HBr is used pattern polysilicon gate electrodes in the manufacture of self-aligned polysilicon gate MOSFETs (metal oxide silicon field effect transistors). These devices are the mainstay of today's integrated circuit industry. The polysilicon gate electrodes are patterned in a deposited conductive layer stack formed over a thin silicon oxide which forms the gate dielectric of the MOSFET. The conductive layer stack typically comprises a bottom undoped polysilicon layer over which a doped polysilicon layer or a layer of a transition metal silicide is deposited to improve the conductivity. The latter configuration is referred to a polycide gate structure. An insulative cap layer is deposited over the conductive layers and the stack is then patterned with a photoresist mask.
The silicon oxide gate layer is extremely thin, typically less than 100 Angstroms and often as thin as 20 Angstroms. The gate electrode must be patterned with an anisotropic plasma etch such as RIE. The etching must stop on the thin silicon oxide layer without penetrating it. Finally, an over-etch period must be employed to assure that all vestiges of polysilicon are removed in order to avoid subsequent shorts. In order to meet these stringent requirements a polysilicon etchant which has a very high polysilicon-to-silicon oxide selectivity must be used. Etchants containing HBr have are most widely preferred to meet these criteria. However, upon completion of the silicon etching, bromine remains strongly chemisorbed on the exposed silicon oxide surfaces and causes the same corrosion problems, yield losses, and safety concerns which accompany the silicon trench etching processes described above.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a method for removing residual HBr from a plasma etching tool after a silicon etching operation without requiring extensive pumping or baking.
It is another object of this invention to provide a method for reducing the cycle time of a silicon etching tool wherein HBr or other halogen containing agent is employed which can cause corrosion of metal surfaces of the tool which may become exposed to moisture during loading and unloading.
It is yet another object of this invention to thoroughly remove bromine chemisorbed on a wafer after processing with HBr before said wafer is exposed to atmospheric moisture.
It is another object of this invention to provide a method for improving process yield of a plasma etching tool wherein wafers are loaded and unloaded through a load lock.
These objects are accomplished by subjecting the wafer to gas flow containing H
2
O after the trench etching process is completed. In the process, residual HBr and chemisorbed bromine or other halogen containing species from the silicon etching, are entirely removed from the wafer prior before the wafer is transferred into the load lock. The halogen removal is accomplished in an intermediate transfer chamber located within the etching tool. After etching, the wafer is moved out of the main etching chamber and into the intermedi

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