Hazard-free clocked master/slave flip-flop

Details Hazard-free clocked master/slave flip-flop Hazard-free clocked master/slave flip-flop

1976-12-10

1978-02-07

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307218, 307269, 328206, H03K 3286

Patent

active

040728692

ABSTRACT:
The clocked flip-flop circuit of the present invention is one that cannot be caused to yield an erroneous output upon a skew in a clock pulse or, equivalently, the offset of such pulse with respect to its complement. The disclosed flip-flop circuit is comprised of a J-K master portion and a D latch slave portion. Each portion includes a gate having no operative functional definition as respects provision of an output under normal operating conditions of the circuit. In normal operation, the circuit, exclusive of the additional gates, provides HOLD, SET/RESET and TOGGLE functions according as the setting of J and K inputs. Upon skew of a clock pulse, the additionally provided gates insure integrity of the outputs corresponding to the J and K settings by defining a failure mode of operation of the flip-flop, independent of the clock.

REFERENCES:
patent: 3535544 (1970-10-01), De Troye
patent: 3575608 (1971-04-01), Barth
patent: 3588546 (1971-06-01), Lagemann
patent: 3609569 (1971-09-01), Todd
patent: 3701104 (1972-10-01), Wiseman
patent: 3917961 (1975-11-01), Reed
patent: 3993918 (1976-11-01), Sinclair

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