Having write merge and data override capability for a superscala

Details Having write merge and data override capability for a superscala Having write merge and data override capability for a superscala

1993-09-27

1998-10-20

Lall, Parshotam S.

395393, 39580023, G06F 900

Patent

active

058260692

ABSTRACT:
A mechanism and method for use in a superscalar microprocessor for storing into a register file within a single clock cycle, the results of multiple instructions (or micro-ops) that become available for storage into the register file at the same instant thus avoiding a microprocessor stall. The present invention may store, during a single clock cycle, results of up to four instructions that become available at the same time and that may target the same register, flag or portion thereof. By storing the results of the instructions (that are executed in parallel) at the same time, the present invention avoids inefficient stalls otherwise associated with prior art microprocessors when to or more instructions (or micro-ops) target the same register, register portion, or flag. The present invention utilizes a special decoder scheme, coupled with merge and priority logic to store the results into the real register file within a single clock cycle. Results of multiple instructions that may target the same register or the same register portion (i.e., data prioritizations are required) or results that target different portions of the same register (i.e., data merges are required) are supplied into the register file during one clock period. The same is true for explicit and implicit flag updates.

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