Hardwired pipeline processor for logic simulation

Details Hardwired pipeline processor for logic simulation Hardwired pipeline processor for logic simulation

1987-06-26

1990-04-10

Lall, Parshotam S.

Boots, shoes, and leggings

3642212, 3642643, G06F 1516, G06F 1560

Patent

active

049166476

ABSTRACT:
Computer for implementing an event driven algorithm which utilizes a master processor and a plurality of processors arranged in modules, wherein the processors within the module are capable of operating independently of each other. The various modules are also capable of operating independently of each other and communicate with each other and the host unit by a unidirectional token ring bus. A specialized hardwired processor design is implemented to provide a pipelined flow of data to provide a more rapid algorithm simulation.

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