Hardware system verification environment tool

Details Hardware system verification environment tool Hardware system verification environment tool

1996-04-02

1998-10-13

Teska, Kevin J.

Boots, shoes, and leggings

371 221, 395500, G06F 1300

Patent

active

058222260

ABSTRACT:
A random verification environment for verifying a semiconductor device includes a hardware engine programmed to include a random input generator that builds a set of test vectors. A first memory connected between the hardware engine and the semiconductor device stores the set of test vectors and supplies the set of vectors to the semiconductor device under the control of a first state machine generated by the hardware device. A second memory connected to the semiconductor device receives output signals from the semiconductor device in response to input test vectors. A random test iterator in the hardware engine provides a first state machine and also provides a second state machine that writes the signals output from the semiconductor device to the second memory. The test vectors are input to the semiconductor device at a rate equal to the operating rate of the semiconductor device. An expected output generator is arranged to receive the test vectors from the first memory. An output comparator is arranged to receive outputs from the expected output generator and from the second memory and to record whether the output of the semiconductor device for each test vector is the expected output provided by the expected output generator.

REFERENCES:
patent: 5202889 (1993-04-01), Aharon et al.
patent: 5438673 (1995-08-01), Court et al.
patent: 5488573 (1996-01-01), Brown et al.
patent: 5568407 (1996-10-01), Hass et al.

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