Hardware system for genlocking

Details Hardware system for genlocking Hardware system for genlocking

1997-03-31

2002-08-27

Shalwala, Bipin (Department: 2673)

Computer graphics processing and selective visual display system

Display driving control circuitry

Display power source

C345S204000, C348S510000, C348S500000, C348S540000, C348S544000

Reexamination Certificate

active

06441812

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer graphics, and more particularly to the generation of a refresh rate in a computer graphics system.
2. Description of the Related Art
Referring to
FIG. 1
, a conventional graphics subsystem
10
is shown. The graphics subsystem
10
includes a graphics controller
14
having a clock logic unit
16
, video digital to analog convertor (VDAC)
18
and video input unit
20
. The graphics controller
14
communicates with a host processor, such as a microprocessor, by way of a host bus HBUS. The graphics controller receives instructions, data to be processed for display, and/or graphics data from the host.
The graphics controller
14
interfaces with a graphics memory
22
through a control line CTRL and a data bus, bus RDATA. The graphics controller
14
sends and receives graphics data to and from the graphics memory
22
through a random access port in the graphics memory
22
over bus RDATA. The graphics memory
22
is typically a frame buffer having banks of random access memory (RAM). The graphics memory
22
stores the graphics data to be displayed, generally in bit-mapped or other well-known formats.
When the graphics data is to be displayed, the graphics memory
22
outputs the stored graphics data onto bus RDATA to the video input unit
20
which communicates the graphics data to the VDAC
18
. VDAC
18
compares the digital values of the graphics data to a look-up table that contains the matching analog voltage levels for three primary colors needed to create the indicated color, which in this embodiment are red, green and blue (RGB). The VDAC
18
then converts the digital video data into the analog values of the RGB colors, and outputs the analog values on the R, G, and B lines respectively to the monitor
24
for display.
The graphics subsystem
10
also includes a high speed clock generator
12
, which typically includes a crystal oscillator. The high speed clock generator
12
outputs a clock signal CLK at a set frequency to the clock logic unit
16
in the graphics controller
14
. The clock logic unit
16
generates various clock signals which control the timing of the operations of the graphics subsystem
10
. For example, the clock logic unit
16
generates a clock signal MCLK that is inputted to the graphics memory
22
. The MCLK signal controls the rate at which the graphics memory
22
presents the graphics data onto bus RDATA. The clock logic unit
16
outputs a clock signal at the same frequency to the video input unit
20
so that it may correctly latch the graphics data from the bus RDATA. The clock logic unit
16
also generates a clock signal to VDAC
18
which controls the pixel rate of the graphics data received from the video input unit
20
.
Finally, the clock logic unit
16
generates two clock control signals: a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC. The VSYNC and HSYNC signals control the refresh rate of the monitor
24
, i.e. how frequently the monitor's image is redrawn.
In the conventional system of
FIG. 1
, the clock signals for the monitor
24
, the graphics controller
14
and the graphics memory
22
are all derived from the CLK signal generated by the clock generator
12
. In order to obtain a refresh rate of 60 Hz, for instance, for a 1024×768 resolution monitor, the VDAC
18
must convert one pixel of data every
21
nanoseconds, i.e., a pixel data rate of 47 MHZ. In order to meet this data rate, clock logic unit
16
may apply a higher clock rate of 47 MHZ to VDAC
18
than to the graphics memory
22
by dividing the signal CLK from clock generator
12
, as is discussed in more detail in U.S. Pat. No. 5,488,393, issued Jan. 30, 1996 and entitled, “High-Speed Video Display System,” which is incorporated by reference herein.
A problem arises however, when the input graphics data into the graphics memory
22
originates from a source other than the graphics controller
14
. New technology now allows the integration of a computer system with a second device such as a television, telephone, laser disk player, etc. The video data from this secondary source is displayed on a computer monitor along with graphics data from the graphics controller
14
.
The display of this video data creates a problem when the video data has a different refresh rate from the 60 Hz refresh rate of the graphics controller. For example, a television signal such as the ITU-BTU System M (NTSC) signal typically has a refresh rate of 59.94 Hz. In a computer/television integrated device, the television signal is converted into digital graphics data for storage in a graphics memory for display on a monitor. The 59.94 Hz refresh rate of the television signal must be reconciled with the 60 Hz refresh rate of the graphics subsystem, otherwise the video fields will be dropped or repeated. This dropping of fields results in jerky movements of items on the display of the monitor, also known as syncopation artifacts.
One solution is to reprogram the refresh rate of the graphics subsystem to 59.94 Hz to match the refresh rate of the television signal. However, the refresh rate of the television signal varies somewhat from the 59.94 Hz rate through time. This variation of the television signal would thus create a mismatch in refresh rates. In addition, video data from various other secondary sources may have different refresh rates, none of which match each other or the programmed refresh rate of the graphics subsystem.
Because of this mismatch between refresh rates of the graphics subsystem and a second source of video data, a need has arisen in the industry for an external control of the refresh rate of the graphics subsystem.
SUMMARY OF THE INVENTION
The present invention is directed to a computer system having a graphics controller with a first refresh rate and a first horizontal synchronization signal; a secondary source of video data having a second refresh rate and a second horizontal synchronization signal; and a genlock unit for reconciling the first refresh rate of the graphics controller with the second refresh rate of the secondary source. The genlock unit outputs a clock signal with a frequency modulated to reconcile the first refresh rate and the second refresh rate by monitoring the phase differences of the first horizontal synchronization signal and the second horizontal synchronization signal in response to a first control signal and outputs a clock signal at a frequency corresponding to a selected clock frequency in response to a second control signal.
The present invention is also directed to a method of generating a clock signal for a graphics controller in a computer system. The method includes the steps of determining that the computer system is operating in a first one of two modes, and in response to this step, generating the clock signal for the graphics controller at a frequency modulated to reconcile a refresh rate of the graphics controller and a refresh rate from a secondary source by monitoring the differences of the horizontal synchronization signal of the graphics controller and the horizontal synchronization signal of the secondary source. The invention further includes the step of determining that the computer system is operating in a second one of two modes, and in response thereto, generating a clock signal for the graphics controller at a frequency corresponding to a predetermined frequency.


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