Boots – shoes – and leggings
Patent
1993-06-10
1996-11-05
Kriess, Kevin A.
Boots, shoes, and leggings
364488, 364578, 3642323, 3649338, 364DIG1, 395800, G06F 1520
Patent
active
055727085
ABSTRACT:
In a logic simulator for simulating a logic circuit described by sentences, each specifying at least one operation and at least two variables which should be subjected to the operation, a model memory memorizes operators for carrying out the operations for the sentences. A variable memory memorizes initial values of the variables for the sentences. A sentence calculating unit calculates one of the sentences as a current sentence at a time to produce a result of calculation by using those of the operators and the initial values which are related to the current sentence. A data or result memory memorizes previous data or initial result values calculated before calculation of the current sentence. The result of calculation is substituted for those of the previous data or the initial result values which are related to the current sentences. Preferably, a flag memory is used to memorize, in correspondence to the respective sentences, flags indicative of whether or not the initial values are changed while simulation is in progress. One of the sentences is selected as the current sentence only when the flag indicates a change for the sentence in question. More preferably, the sentence calculating unit is accompanied by the input and output first-in first-out memories for enabling calculation of a plurality of successive ones of the sentences.
REFERENCES:
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4541071 (1985-09-01), Ohmori
patent: 4656580 (1987-04-01), Hitchcock, Sr. et al.
patent: 4725975 (1988-02-01), Sasaki
patent: 4775950 (1988-10-01), Terada et al.
patent: 4782440 (1988-11-01), Nomizu et al.
patent: 4862347 (1989-08-01), Rudy
patent: 4891773 (1990-01-01), Ooe et al.
patent: 4914612 (1990-04-01), Beece et al.
patent: 4918594 (1990-04-01), Onizuka
patent: 4964056 (1990-10-01), Bekki et al.
Tarasaki et al, Block-Level Hardware Logic Simulation Machine, IEEE Transactions on CAD, vol CAD-6, No.: 1, Jan./1987, pp. 46-54.
Kriess Kevin A.
NEC Corporation
Toplu Lucien
LandOfFree
Hardware simulator capable of dealing with a description of a fu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hardware simulator capable of dealing with a description of a fu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hardware simulator capable of dealing with a description of a fu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2022928