Hardware simulator capable of dealing with a description of a fu

Details Hardware simulator capable of dealing with a description of a fu Hardware simulator capable of dealing with a description of a fu

1995-05-01

2000-12-05

Teska, Kevin J.

Data processing: structural design, modeling, simulation, and em

Emulation

Of instruction

703 28, 703 14, G06F 944

Patent

active

061579041

ABSTRACT:
In a logic simulator for simulating a logic circuit described by sentences, each specifying at least one operation and at least two variables which should be subjected to the operation, a model memory memorizes operators for carrying out the operations for the sentences. A variable memory memorizes initial values of the variables for the sentences. A sentence calculating unit calculates one of the sentences as a current sentence at a time to produce a result of calculation by using those of the operators and the initial values which are related to the current sentence. A data or result memory memorizes previous data or initial result values calculated before calculation of the current sentence. The result of calculation is substituted for those of the previous data or the initial result values which are related to the current sentences. Preferably, a flag memory is used to memorize, in correspondence to the respective sentences, flags indicative of whether or not the initial values are changed while simulation is in progress. One of the sentences is selected as the current sentence only when the flag indicates a change for the sentence in question. More preferably, the sentence calculating unit is accompanied by the input and output first-in first-out memories for enabling calculation of a plurality of successive ones of the sentences.

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Augustin et al., "Verification of VHDL Desing Using VAL," AMC/IEEE 1988, pp. 48-53.

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