Hardware simulation using a test scenario manager

Details Hardware simulation using a test scenario manager Hardware simulation using a test scenario manager

2001-11-27

2009-12-01

Shah, Kamini (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S020000

Reexamination Certificate

active

07627462

ABSTRACT:
A hardware simulation and validation system is provided using a plurality of signal interface controllers to exchange stimulus and response signals with a hardware simulation. The action of the signal interface controllers is coordinated by a test scenario manager which exchanges test scenario controlling messages with the signal interface controllers. The test scenario controlling messages specify simulation actions to be performed and when those simulation actions are to be performed.

REFERENCES:
patent: 5710934 (1998-01-01), Bona et al.
patent: 5991533 (1999-11-01), Sano et al.
patent: 6002861 (1999-12-01), Butts et al.
patent: 6006028 (1999-12-01), Aharon et al.
patent: 6134516 (2000-10-01), Wang et al.
patent: 6295623 (2001-09-01), Lesmeister et al.
patent: 6678645 (2004-01-01), Rajsuman et al.
patent: 2001/0042226 (2001-11-01), Dzoba et al.
patent: 2002/0002698 (2002-01-01), Hekmatpour
patent: 2002/0019969 (2002-02-01), Hellestrand et al.
patent: 2002/0040288 (2002-04-01), Yamoto et al.
patent: 2002/0042897 (2002-04-01), Klein et al.
patent: 2003/0182642 (2003-09-01), Schubert et al.
patent: 2005/0076314 (2005-04-01), Matsui et al.
patent: 2005/0100032 (2005-05-01), Patiejunas
patent: 2005/0125754 (2005-06-01), Schubert et al.
patent: 2005/0143630 (2005-06-01), Darby et al.
patent: 2005/0143968 (2005-06-01), Odom et al.
patent: 2005/0144577 (2005-06-01), Devins et al.
patent: 2005/0149898 (2005-07-01), Hakewill et al.
patent: 2005/0193280 (2005-09-01), Schubert et al.
“Towards Design And Validation Of Mixed-Technology SOCs”, S. Mir , B. Chariot , G. Nicolescu , R Coste , E Parrain , N. Zergainoh, B. Courtois , A. Jerraya and M. Rencz. 2000.
“An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC”. Amer Baghdadi Damien Lyonnard Nacer-E. Zergainoh Ahmed A. Jerraya. 2001.
“Nuts and Bolts of Core and SoC Verification”. Ken Albin. 2001.

Affiliated with

Also associated with

Rating

Hardware simulation using a test scenario manager does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hardware simulation using a test scenario manager, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hardware simulation using a test scenario manager will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4077154