Hardware semaphores in a multi-processor environment

Details Hardware semaphores in a multi-processor environment Hardware semaphores in a multi-processor environment

1990-10-11

1994-01-04

Chun, Debra A.

Boots, shoes, and leggings

364DIG2, 3649314, 36493148, 3649401, G06F 1314, G06F 1516

Patent

active

052768864

ABSTRACT:
In a computer system having at least two processors, each processor having an associated memory, the processors being coupled to one another through an interface unit by means of a bus, hardware semaphores to regulate access to shared resources are disclosed. Each semaphore is one bit wide and can be written to obtain the desired state. When reading the semaphore, if the contents is a one, then a one is returned. If the content is zero, a zero is returned but the semaphore is automatically reset to one.

REFERENCES:
patent: 4380798 (1983-04-01), Shannon et al.
patent: 4594657 (1986-06-01), Byrns
patent: 4725946 (1988-02-01), Prange et al.
patent: 5050072 (1991-09-01), Earnshaw et al.

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