Hardware queue management with distributed linking information

Details Hardware queue management with distributed linking information Hardware queue management with distributed linking information

2008-07-29

2011-11-15

Shah, Chirag (Department: 2477)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

Reexamination Certificate

active

08059670

ABSTRACT:
A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the memory space of the packet descriptors. A linking memory is implemented in the same integrated circuit as the processor, and has entries corresponding to the descriptor index values. Each entry can store the next descriptor index in a packet queue, to form a linked list of packet descriptors. Queue manager logic receives push and pop requests from host applications, and updates the linking memory to maintain the queue. The queue manager logic also maintains a queue control register for each queue, including head and tail descriptor index values.

REFERENCES:
patent: 7523284 (2009-04-01), Wilson
patent: 2003/0182507 (2003-09-01), Naffziger et al.
patent: 2005/0147038 (2005-07-01), Chandra et al.
patent: 2005/0163141 (2005-07-01), Katayama

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