Hardware process scheduler and processor interrupter for paralle

Details Hardware process scheduler and processor interrupter for paralle Hardware process scheduler and processor interrupter for paralle

1993-02-01

1995-01-03

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG1, 3642818, 3642287, 3642301, 3642316, G06F 946

Patent

active

053794281

ABSTRACT:
A general-purpose device for scheduling and dispatching processes having variable processing priorities in parallel processing computer systems having multiple processors. The device comprises a plurality of cluster schedulers for scheduling processes on processor clusters and a processor interrupter for interrupting the processors. The cluster scheduler has an insert register queue that queues processes for execution on the processors. The cluster scheduler outputs the most significant process priority number awaiting execution. Processors access the cluster scheduler output in order to determine the next process to execute. The processor interrupter is initiated by the cluster scheduler whenever a new process is queued by the cluster scheduler. The processor interrupter compares the priority number of the active processes executing on the processors with the cluster scheduler output, and interrupts the processor if it is executing a process with a priority number of lesser value than the cluster scheduler output.

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