Hardware multiprocess scheduler in a graphics rendering processo

Details Hardware multiprocess scheduler in a graphics rendering processo Hardware multiprocess scheduler in a graphics rendering processo

1990-09-14

1993-11-23

Richardson, Robert L.

395163, 395164, 395375, 395575, 395650, G06F 1520

Patent

active

052652033

ABSTRACT:
An integrated hardware multiprocess scheduler for controlling a plurality of concurrently operating graphics generating subsystems required for the generation of display signals for a graphics rendering processor. In so doing, the hardware scheduler controls the operations of these subsystems in parallel, while incorporating in hardware, certain aspects of a software operating system. This feature promotes functional independence between the various controlled subsystems and promotes communication between them. Such independence is accomplished by the structure of the scheduler which is set up so that each of the controlled subsystems is connected to a common status/enable bus in parallel with the other controlled subsystems and each of them is operationally independent of the others. Depending on the instructions received, the scheduler enables and disables one or more of these subsystems at essentially the same time. This architecture supports zero overhead scheduling and effective teaming together of these independent systems.

REFERENCES:
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patent: 4916301 (1990-04-01), Mansfield et al.
patent: 5003496 (1991-03-01), Hunt, Jr. et al.
patent: 5046023 (1991-09-01), Katsura et al.

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