Hardware multiplication of scaled integers

Details Hardware multiplication of scaled integers Hardware multiplication of scaled integers

1998-11-05

2000-12-12

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708620, G06F 738, G06F 752

Patent

active

061611190

ABSTRACT:
A scaling multiplier circuit in accordance with the invention includes a multiplier circuit, a carry calculation circuit, a logic circuit, and an adder circuit. The multiplier circuit produces a 16-bit product of two 8-bit input numbers. The 16-bit product has bits m(15:0). The carry calculation circuit produces a first carryout bit from a sum of a first number consisting of bits m(6:0), a second number consisting of bits m(14:8), and a third number consisting of bit m(7). The logic circuit produces intermediate carryout bits from a sum of bit m(7m), m(15), the first carryout bit, and a constant bit having a value of "1". The adder circuit produces the actual scaled product by summing the intermediate carryout bits and a fourth number consisting of bits m(15:8).

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Blinn, James F., "Three Wrongs Make A Right", "IEEE Computer Graphics and Applications", Nov. 1995, vol. 15, No. 6, pp. 90-93.

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