Hardware matrix computation for wireless receivers

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

active

07974997

ABSTRACT:
In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.

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patent: 2006/0101245 (2006-05-01), Nair et al.
patent: 2007/0038843 (2007-02-01), Trivedi et al.

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