Hardware logic simulator

Details Hardware logic simulator Hardware logic simulator

1985-03-01

1987-09-29

Gruber, Felix D.

Boots, shoes, and leggings

307465, 364716, 364900, G06F 1520, G06F 1560, H03K 19088

Patent

active

046972412

ABSTRACT:
Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprises a plurality of hardware gates, each of which is programmable so as to correspond to and emulate an element in said logic circuit. Each hardware gate has an output and at least two inputs. A selectively operable interconnection system is provided for establishing a connection between the output of any hardware gate and an input of any hardware gate. A multiplexing system is also provided for operating the interconnection system and determining which, and when, each connection is made between the output of any hardware gate and an input of any hardware gate.

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Yau et al., "Universal Logic Circuits and Their Modular Relizations," Spring Joint Computer Conference, 1968, pp. 297-305.
Pp. 127-138 of Electronic Design of Nov. 10, 1983.
Papers 7.1, 7.2 and 7.3 presented at the 19th Design Automation Conference of the IEEE in 1982.

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