Hardware interpretive mode microprocessor

Details Hardware interpretive mode microprocessor Hardware interpretive mode microprocessor

1979-07-13

1982-04-06

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 930

Patent

active

043239633

ABSTRACT:
In a data processor system comprising memory means containing subroutines each having low level instructions with the last instruction being an INTERPRET instruction, and high level language instructions which point to the starting addresses of said subroutines, a hardware high level language interpret capability comprising first and second program counter means which point respectively to said high level language instructions and to said subroutine instructions, and control and timing means responsive to an INTERPRET instruction to load said second program counter means with the subroutine address contained in the high level language instruction pointed to by said first program counter means. Said second program counter means is responsive to said control and timing means to execute the instructions in said subroutine.

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