Hardware interface to a high-speed multiplexed link

Details Hardware interface to a high-speed multiplexed link Hardware interface to a high-speed multiplexed link

1990-07-11

1992-08-04

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 60, H04J 324

Patent

active

051365847

ABSTRACT:
A link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.

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T1S1 Technical Sub-Committee Broadband Aspects of ISDN, Baseline Document, Feb., 1990, ANSI document T1S1/90-001.

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