Hardware instruction scheduler for short execution unit latencie

Details Hardware instruction scheduler for short execution unit latencie Hardware instruction scheduler for short execution unit latencie

1996-03-07

1998-11-10

Bowler, Alyssa H.

395390, 395392, 395393, 39580023, G06F 906

Patent

active

058357459

ABSTRACT:
A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

REFERENCES:
patent: 4807115 (1989-02-01), Torng
patent: 4847755 (1989-07-01), Morrison et al.
patent: 5021945 (1991-06-01), Morrison et al.
patent: 5202975 (1993-04-01), Rasbold et al.
patent: 5247628 (1993-09-01), Grohoski
patent: 5251306 (1993-10-01), Tran
patent: 5313551 (1994-05-01), Labrouse et al.
patent: 5371684 (1994-12-01), Iadonato et al.
patent: 5509130 (1996-04-01), Trauben et al.
patent: 5517628 (1996-05-01), Morrison et al.
Gao et al; "An Efficient Pipelined Dataflow Processor Architecture"; IEEE; 1988; pp. 368-373.
Moore et al., "IBM Single Chip RISC Processor (RSC)", Computer Design--ICCD '92, IEEE, pp. 200-204, 1992.
Two-Level Adaptive Training Branch Prediction Yeh et al. International Symposium on Microarchitecture After Nov. 18-20, 1991 Paper # 0-89791-460-0/91/0011/0051.
Instruction Reordering for Fork-Join Parallelism, After Jun. 20-22, 1990 Paper # 0-89791-364-7/90/0006/0322.
Alternative Implementations of Two-Level Adaptive Branch Prediction, Yeh, et al. The 19th Annual Symposium on Computer Architecture May 1992.
Dynamic Instruction Scheduling and the Astronautics ZS-1, James E. Smith, Jul. 1989, Computer Magazine.

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