Hardware implemented cache coherency protocol with duplicated di

Details Hardware implemented cache coherency protocol with duplicated di Hardware implemented cache coherency protocol with duplicated di

1988-11-14

1991-06-18

Eng, David Y.

Boots, shoes, and leggings

3642434, 36424341, G06F 1212, G06F 1300

Patent

active

050253654

ABSTRACT:
This disclosure describes a snooping coherency protocol for a multiprocessor network wherein every processor has its own private cache and bus interface means and the network is connected via a common system bus. Each processor has its own cache directory and image directory that duplicate each other non-atomically. The snooping protocol utilizes the duality of directories coupled with the non-atomicity of directory updates to maximize processor-cache availability and minimize processor-cache access times thus supporting high performance architectures.

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Censier, "A New Solution to Coherence Problems in Multi-Cache System", 12/12/78, IEEE Transactions on Computers, vol. C-27, pp. 1112-1118.

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