Hardware implementation of network testing and performance...

Details Hardware implementation of network testing and performance... Hardware implementation of network testing and performance...

2006-03-22

2010-02-23

Duong, Frank (Department: 2416)

Multiplex communications

Diagnostic testing

Fault detection

Reexamination Certificate

active

07668107

ABSTRACT:
An embodiment of the present invention offloads the generation and monitoring of test packets from a Central processing Unit (CPU) to a dedicated network integrated circuit, such as a router, bridge or switch chip associated with the CPU. The CPU may download test routines and test data to the network IC, which then generates the test packets, identifies and handles received test packets, collects test statistics, and performs other test functions all without loading the CPU. The CPU may be notified when certain events occur, such as when throughput or jitter thresholds for the network are exceeded.

REFERENCES:
patent: 6658480 (2003-12-01), Boucher et al.
patent: 7411957 (2008-08-01), Stacy et al.
patent: 2006/0002292 (2006-01-01), Chang et al.
patent: 2006/0002386 (2006-01-01), Yik et al.
Mohan, Dinesh, Nortel Networks, “802.1ag—Connectivity Fault management Tutorial—Part 1” (Jul. 12, 2004) pp. 1-21.
Katz, D. and Ward, D., “Bidirectional Forwarding Detection” The Internet Society (© 2004), pp. 1-40.

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