Hardware implementation of maximum likelihood sequence...

Details Hardware implementation of maximum likelihood sequence... Hardware implementation of maximum likelihood sequence...

2007-07-24

2007-07-24

Kim, Kevin (Department: 2611)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C714S794000

Reexamination Certificate

active

10454883

ABSTRACT:
A coding/decoding trellis structure circuit included in a maximum likelihood sequence estimator (MLSE) sub-receiver having one or more distance calculation units (distus) responsive to equalized data generated by said MLSE sub-receiver from wireless transmission of transmitted data, said distu further responsive to MLSE codewords for processing the same, said equalized data including one or more equalized data chips and each of said MLSE codewords including one or more MLSE codeword chips, each of said distus for processing an equalized data chip and an MLSE codeword chip to generate a chip output, said distu for using said chip output to generate distance measures, a distance measure being the distance between said equalized data and said MLSE codeword, in accordance with an embodiment of the present invention. The coding/decoding trellis structure circuit further including one or more accumulator devices responsive to said chip output and said distance measures for storing the same for use by said one or more distus. The coding/decoding trellis structure circuit further including one or more comparator devices responsive to said chip output and said distance measures for processing the same to generate a decoded equalized data, said MLSE sub-receiver using said decoded equalized data to generate a decoded transmitted data.

REFERENCES:
patent: 6035007 (2000-03-01), Khayrallah et al.
patent: 2003/0033574 (2003-02-01), Vasic

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