Hardware implementation of a decimating finite impulse...

Details Hardware implementation of a decimating finite impulse... Hardware implementation of a decimating finite impulse...

1998-08-17

2003-08-05

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Equalizers

Automatic

C708S300000

Reexamination Certificate

active

06603812

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to finite impulse response (FIR) digital filters used in signal sample rate conversion (i.e., decimation filters). More particularly, the present invention relates to a compact hardware implementation for an FIR decimating filter used in oversampling analog-to-digital converters.
BACKGROUND OF THE INVENTION
Decimation filters commonly are used for digital signal processing in such fields as communications, instrumentation, data acquisition, audio-video, industrial control, etc. The input signal SIG
in
to a decimation filter is a digital signal of limited bandwidth F
s
/2, and is represented as a stream of digital samples at a rate F
a
. The decimation filter generates an output sequence SIG
out
that is a digital signal of limited bandwidth F
o
/2, and is represented as a stream of digital samples at a rate F
o
. The input rate F
s
typically is an integer multiple of the output rate F
o
. The decimation ration N is defined as N=F
a
/F
o
. The decimation filter operates at a clock rate F
elk
that typically is an integer multiple of both F
s
and F
o
.
An FIR decimation filter is represented by a coefficient sequence h(n) having a finite length L. The filter generates output samples S
out
by convolving the input sequence SIG
in
of unbounded length with the coefficient sequence h(n). Output sequence SIG
out
is formed by selecting every N-th sample of output samples S
out
. The remaining N-1 output samples S
out
are discarded.
In oversampling analog-to-digital converters, a decimation filter typically is used to lower the sampling rate of a signal generated by a delta-sigma modulator. The decimation filter also must adequately attenuate quantization noise generated by the modulator. If the analog-to-digital converter implements double integration sigma-delta modulation, a decimation filter having a Sinc
3
(N&ohgr;T/2) frequency response is desirable, where T=1/F
s
. For other analog-to-digital converter designs, decimation filters having higher order (e.g., Sinc
4
(N&ohgr;T/2) and higher) frequency response are desirable.
As the filter length L increases, the size of the coefficient sequence h(n) becomes very large, and the circuitry related to it occupies a significant area. Traditionally, the sequence h(n) is stored in random access memory (RAM) or read only memory (ROM), and a dedicated state machine retrieves the coefficients from memory as necessary. Although such an approach provides flexibility with respect to coefficient values, the required circuitry is nevertheless prohibitively large for many applications. For example, an FIR filter with L=1024 and a coefficient word size of 32 bits requires a total coefficient memory of 32K bits.
To eliminate the need for a RAM or ROM storage array for the filter coefficients, investigators have proposed calculating the coefficient sequence h(n) in real-time. For example, James C. Candy et al., “Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator,” IEEE Trans. Commun., vol. COM-24, pp. 1268-1275, Nov. 1976, describes hardware that generates the h(n) sequence for decimation filters having Sinc(N&ohgr;T/2), Sinc
2
(N&ohgr;T/2) and intermediate derivative frequency response characteristics. Candy's circuits, however, become increasingly complex and restrictive for higher order filters.
In addition, Hanafy Meleis and Pierre Le Fur, “A novel Architecture Design for VLSI Implementation of an FIR Decimation Filter,” IEEE Proc. ICASSP '85, pp. 1380-1383, March 1985, describes hardware that generates the h(n) sequence for a decimation filter having a Sinc
3
(N&ohgr;T/2) frequency response. The described hardware, however, is limited to a Sinc
3
(N&ohgr;T/2) filter.
In view of the foregoing, it would be desirable to provide a compact hardware implementation of an FIR digital decimation filter.
It also would be desirable to provide an apparatus for generating in real-time the coefficients of a digital decimation filter for a large class of complex decimation filters, of which the Sinc
4
(N&ohgr;T/2) filter is a specific example.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide a compact hardware implementation of an FIR digital decimation filter.
It also is an object of this invention to provide methods and apparatus for generating in real-time the coefficients of a digital decimation filter for a large class of complex decimation filters, of which the Sinc
4
(N&ohgr;T/2) filter is a specific example.
In accordance with these and other objects of the present invention, methods and apparatus for generating coefficients of a digital decimation filter are described that use a predetermined input sequence x(n) of Length L, and generates L filter coefficients h(n). The predetermined input sequence x(n) is very simple, and may be used to generate a much more complex output sequence h(n) with minimal computational complexity.
The coefficient generator includes at least one adder and accumulator that receives the input sequence and generates the output sequence. In one exemplary embodiment, the at least one adder and accumulator includes a multi-bit adder and a multi-bit accumulator register. In a first alternative embodiment, the at least one adder and accumulator includes a binary full adder and a serial shift register. In a second alternative embodiment, the at least one adder and accumulator includes a plurality of interleaved binary full adders and serial shift registers.
In addition, methods and apparatus for digitally filtering an input sequence are described that generate the filter coefficients h(n) and perform the filtering operation in real-time.


REFERENCES:
patent: 4872129 (1989-10-01), Pfeifer et al.
patent: 5357252 (1994-10-01), Ledzius et al.
patent: 5408235 (1995-04-01), Doyle et al.
patent: 5903232 (1999-05-01), Zarubinsky et al.
Steven R. Norsworthy et al., “Decimation and Interpolation for &Dgr;&Egr; Conversion,” Delta-Sigma Data Converters, Steven R. Norsworthy et al. eds., Ch. 13, pp. 406-444, IEEE Press 1997.
James C. Candy et al., “Oversampling Methods for A/D and D/A Conversion,” Oversampling Delta-Sigma Converters, Steven R. Norsworthy et al. eds., pp. 1-25, IEEE Press 1992.
Max W. Hauser, “Principles of Oversampling A/D Conversion,” J. Audio Eng. Soc., vol. 39, No. 1/2, pp. 3-26, Jan./Feb. 1991.
Hanafy Meleis et al., “A Novel Architecture Design for VLSI Implementation of an FIR Decimation Filter,” IEEE Proc. ICASSP '85, pp. 1380-1383, Mar. 1985.
James C. Candy et al., “Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator,” IEEE Trans. Commun., vol. COM-24, pp. 1268-1275, Nov. 1976.

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