Hardware implementation of 2 line/11 element predictor

Details Hardware implementation of 2 line/11 element predictor Hardware implementation of 2 line/11 element predictor

1981-08-17

1984-01-10

Britton, Howard

Facsimile and static presentation processing

Facsimile

Recording apparatus

340347DD, 382 41, H04N 141, H03K 13243

Patent

active

044255829

ABSTRACT:
A predictor bit pattern comprising selected bits of the current and previous raster scan lines and a method of predicting a plurality of bits per clock are disposed. Generally, a predictor is used prior to the encoding of data to increase the compression. The current bit in a bit stream is compared to the predicted value and a one is output when the two values are not equal. An efficient predictor will reduce the number of ones in a bit stream, which increases the zero run lengths and increases the efficiency of a run length encoding system. The described bit pattern contains bits close to the current bit to efficiently predict text data, bits distant from the current bit to efficiently predict halftone data, and ignores a plurality of intermediate bits to reduce hardware costs. A two step process is also described to allow a plurality of bits to be predicted in parallel. A circuit for performing this process comprises a buffer for storing the previous and current line data, two registers for holding the previous and current line prediction data patterns and two PROMs for performing the two step prediction.

REFERENCES:
patent: 4028731 (1977-06-01), Arps
patent: 4293920 (1981-10-01), Merola
patent: 4325085 (1982-04-01), Gooch
patent: 4355306 (1982-10-01), Mitchell

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