Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2006-07-18
2006-07-18
Mai, Tan V. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07080110
ABSTRACT:
The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to the structure and linking of a plurality of almost identical processing elements.
REFERENCES:
patent: 5321752 (1994-06-01), Iwamura et al.
patent: 5513133 (1996-04-01), Cressel et al.
patent: 5764554 (1998-06-01), Monier
patent: 2004/0054706 (2004-03-01), Kawamura
patent: 05-068032 (1993-03-01), None
patent: 05-324277 (1993-12-01), None
patent: 09-016379 (1997-01-01), None
patent: 09-274560 (1997-10-01), None
patent: 11-143688 (1999-05-01), None
patent: 11-282351 (1999-10-01), None
patent: 2001-051832 (2001-02-01), None
Kornerup, Peter, “A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms,” IEEE Transactions on Computers, vol. 43, No. 8, Aug., 1994, pp. 892-898.
Chen Chin-Long
Condorelli Vincenzo
Fayad Camil
Cutter Lawrence D.
International Business Machines - Corporation
Mai Tan V.
Scully Scott Murphy & Presser
LandOfFree
Hardware implementation for modular multiplication using a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hardware implementation for modular multiplication using a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hardware implementation for modular multiplication using a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3569314