Patent
1994-09-16
1997-10-14
Tung, Kee M.
395503, 395513, 395523, G06F 1300
Patent
active
056780370
ABSTRACT:
A hardware graphics accelerator (HGA) system which has a source memory element which is loaded to initiate HGA operations operates in two modes: (1) a FIFO mode for normal HGA operations and (2) a recirculate mode for high speed pattern transfers and pattern expands by the HGA. The use of the second mode simplifies the structure and increases the operating speed of the HGA and its associated CPU by eliminating the use of the dedicated pattern registers and pattern control multiplexers of prior art HGA systems.
REFERENCES:
patent: 5486844 (1996-01-01), Randall et al.
Osugi Kevin J.
Starnes Darrell J.
Moy Jeffrey D.
Tung Kee M.
VLSI Technology Inc.
Weiss Harry M.
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