Patent
1993-04-26
1997-08-12
Knepper, David D.
395 212, G10L 300
Patent
active
056574231
ABSTRACT:
A data processing system (10) uses a microprocessor host (12) coupled to a decoding system (14). A hardware filter arithmetic unit block (32) retrieves decoded information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). An address circuit forms several addresses from a single value to accesses multiple sources of data and coefficients simultaneously for use by the hardware filter arithmetic unit.
REFERENCES:
patent: 4394774 (1983-07-01), Widergren et al.
patent: 4644488 (1987-02-01), Nathan
patent: 5097331 (1992-03-01), Chen et al.
patent: 5157488 (1992-10-01), Pennebaker
patent: 5218565 (1993-06-01), Mou et al.
patent: 5233348 (1993-08-01), Pollmann et al.
patent: 5235538 (1993-08-01), Sumi et al.
patent: 5253078 (1993-10-01), Balkanski et al.
patent: 5327520 (1994-07-01), Chen
patent: 5414796 (1995-05-01), Jacobs et al.
Le Gall, "Digital Multimedia Systems", Communications of the ACM, Apr. 1991, vol. 34, No. 4, pp. 47-58.
CD11172-3, "Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 MBits/se", SC29/WG11, MPBG (Moving Pictures Expert Group), Jul. 14, 1992.
Benbassat Gerard
Cyr Kenneth R.
Laczko, Sr. Frank L.
Li Stephen H.
Rowlands Jonathan L.
Donaldson Richard L.
Knepper David D.
Laws Gerald E.
McClure C. Alan
Texas Instruments Incorporated
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