Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
2009-05-01
2011-12-13
Faherty, Corey S (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C712S033000, C345S504000
Reexamination Certificate
active
08078837
ABSTRACT:
A hardware engine control apparatus includes: a plurality of hardware engines (HWEs) connected by a control bus, each of the hardware engines executing a series of different kinds of processing; a host control device that outputs control commands for controlling operation of the HWEs to a subordinate control device; and the subordinate control device that has a register, in which the control commands from the host control device is sequentially set, and outputs the control commands set in the register to the control bus at timing based on a clock signal. The HWEs operate according to the control commands output from the subordinate control device.
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Shen et al.; Modern Processor Design: Fundamentals of Superscalar Processors; Beta Edition; 2002; McGraw-Hill.
Faherty Corey S
Kabushiki Kaisha Toshiba
Turocy & Watson LLP
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