Hardware emulations system with delay units

Details Hardware emulations system with delay units Hardware emulations system with delay units

1995-02-03

1998-08-25

Lall, Parshotam S.

Boots, shoes, and leggings

364580, 39518309, 395800, G06F 1300

Patent

active

057986452

ABSTRACT:
The invention relates to an electronic hardware ASIC (Application Specific Integrated Circuit) prototyper permitting the emulation of integrated circuits or ASICs, so that testing of the component to be generated is possible in the later hardware environment.
There are known in the art emulation systems comprising a matrix of configurable logic blocks, configurable 10 cells and a configurable wiring. These systems emulate the functional behavior only of the desired circuit.
According to the invention, by the addition of programmable delay units into the logic cells, and by the application of programmable coupling fields with delay units to combine the logic modules formed of a multitude of logic cells, it is achieved that the time behavior of an ASIC is considered during emulation, so that a complete emulation is obtained. By purposely setting all inputs to a defined logic state, a fault emulation can be achieved. By the programmable delay units, race problems can be detected.

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