1996-12-19
2000-06-20
Teska, Kevin J.
395293, 395299, 395309, G06F 9455
Patent
active
060787422
ABSTRACT:
The invention features a method and apparatus for use with a computer system having a memory and a bus (e.g., a PCI bus). The bus is monitored for detection of a bus cycle intended for a controller (e.g., a DMA controller) used to transfer data between a bus device and the memory. After detection, the bus device is used to claim the bus cycle and to emulate the response of the controller to the bus cycle.
REFERENCES:
patent: 5099420 (1992-03-01), Barlow et al.
patent: 5564041 (1996-10-01), Matsui et al.
patent: 5673400 (1997-09-01), Kenny
patent: 5708783 (1998-01-01), Yazdy
patent: 5748945 (1998-05-01), Ng
ATI International
Irshadullah M.
Teska Kevin J.
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