Hardware-efficient implementation of dynamic element...

Details Hardware-efficient implementation of dynamic element... Hardware-efficient implementation of dynamic element...

2006-11-07

2006-11-07

Barnie, Rexford (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S144000

Reexamination Certificate

active

07132968

ABSTRACT:
A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0and x1of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ∀1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

REFERENCES:
patent: 5056087 (1991-10-01), Ferguson
patent: 5305004 (1994-04-01), Fattaruso
patent: 5404142 (1995-04-01), Adams et al.
patent: 6124813 (2000-09-01), Robertson et al.
patent: 6304196 (2001-10-01), Copeland et al.
patent: 6466153 (2002-10-01), Yu
patent: 6570521 (2003-05-01), Schofield
patent: 6577261 (2003-06-01), Ho et al.
patent: 6614377 (2003-09-01), Adams et al.
patent: 6720897 (2004-04-01), Wang
patent: 6762702 (2004-07-01), Kwan
Adams, R. et al., “A 113-dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling,”IEEE Journal of Solid-State Circuits33:12:1879-1886 (Dec. 1998).
Annovazzi, M. et al., “A Low-Power 98-dB Multibit Audio DAC in a Standard 3.3-V 0.35-μm CMOS Technology,”IEEE Journal of Solid-State Circuits37:7:825-834 (Jul. 2002).
Baird, R. and Fiez, T., “Improved ΔΣ DAC Linearity Using Data Weighted Averaging,”IEEE, pp. 13-16 (1995), unknown month.
Chen, F. and Leung, B., “Some Observations on Tone Behavior in Data Weighted Averaging,”Proceedings of the IEEE 1998 International Symposium on Circuits and System, 1-500 through 1-503 (May 31-Jun. 3, 1998).
Chen, K. and Kuo, T., “An Improved Technique for Reducing Baseband Tones in Sigma-Delta Modulators Employing Data Weighted Averaging Algorithm Without Adding Dither,”IEEE Transactions on Circuits and Systems- II: Analog and Digital Signal Processing46:1:63-68 (Jan. 1999).
Fishov, A. et al., “Segmented Mismatch-Shaping D/A Conversion,”IEEE, pp. IV-679 through IV-682 (2002), unknown month.
Folgeman, E. and Galton, I., “A Digital Common-Mode Rejection Technique for Differential Analog-to-Digital Conversion,”IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing48:3:255-271 (Mar. 2001).
Galton, I., “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters,”IEEE Transactions on Circuits and System-II: Analog and Digital Signal Processing44:10:808-817 (Oct. 1997).
Grilo, J. et al., “A 12-mW ADC Delta-Sigma Modulator With 80dB of Dynamic Range Integrated in a Single-Chip Bluetooth Transceiver,”IEEE Journal of Solid-State Circuits37:3:271-278 (Mar. 2002).
Jensen, H. and Galton, I., “A Low-Complexity Dynamic Element Matching DAC for Direct Digital Synthesis,”IEEE Transactions on Circuits and Systems- II: Analog and Digital Signal Processing, 45:1:13-27 (Jan. 1998).
Kwan, T. et al., “A Stereo Multibit ΣΔ DAC with Asynchronous Master-Clock Interface,”IEEE Journal of Solid-State Circuits31:12:1881-1887 (Dec. 1996.
Norsworthy, S.R. et al., eds., “Practical Measures for Preventing Idle Tones” inDelta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press, pp. 185-186 (1997).
Radke, R. et al., “A Spurious-Free Delta-Sigma DAC Using Rotated Data Weighted Averaging,”Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, pp. 125-128 (May 16-19, 1999).
Radke, R. et al., “A 14-Bit Current-Mode ΣΔ DAC Based Upon Rotated Data Weighted Averaging,”IEEE Journal of Solid-State Circuits35:8:1074-1084 (Aug. 2000).
Vadipour, M., “Techniques for Preventing Tonal Behavior of Data Weighted Averaging Algorithm in Σ-Δ Modulators,”IEEE Transactions on Circuits and Systems- II: Analog and Digital Signal Processing, Transactions on Circuits and Systems- II: Analog and Digital Signal Processing47:11:1137-1144 (Nov. 2000).
Welz, J. et al., “Simplified Logic for First-Order and Second-Order Mismatch-Shaping Digital-to-Analog Converters,”IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing48:11:1014-1027 (Nov. 2001).
Welz, J. and Galton, I., “A Necessary and Sufficient Condition for Mismatch Shaping in Multi-bit DACS,”IEEE, pp. 1-105 through 108 (2002), unknown month.
Yasuda, A. et al., “A Third-Order Δ-Σ Modulator Using Second-Order Noise Shaping Dynamic Element Matching,”IEEE Journal of Solid-State Circuits33:12:1879-1886 (Dec. 1998).
Zelniker, G. and Taylor, F., “Chapter 7: Multirate Signal Processing” inAdvance Digital Signal Processing: Theory and Applications, Marcel Dekker, Inc., New York, NY, pp. 343-361 (1994), unknown month.

Affiliated with

Also associated with

Rating

Hardware-efficient implementation of dynamic element... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hardware-efficient implementation of dynamic element..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hardware-efficient implementation of dynamic element... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3664196